XC3S100E_06 Datasheet, PDF (133/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Table 93: Output Timing Adjustments for IOB
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Add the
Adjustment
Below
Speed Grade
-5
-4
Single-Ended Standards
LVTTL
Slow 2 mA 5.20 5.41
4 mA 2.32 2.41
6 mA 1.83 1.90
8 mA 0.64 0.67
12 mA 0.68 0.70
16 mA 0.41 0.43
Fast 2 mA 4.80 5.00
4 mA 1.88 1.96
6 mA 1.39 1.45
8 mA 0.32 0.34
12 mA 0.28 0.30
16 mA 0.28 0.30
LVCMOS33
Slow 2 mA 5.08 5.29
4 mA 1.82 1.89
6 mA 1.00 1.04
8 mA 0.66 0.69
12 mA 0.40 0.42
16 mA 0.41 0.43
Fast 2 mA 4.68 4.87
4 mA 1.46 1.52
6 mA 0.38 0.39
8 mA 0.33 0.34
12 mA 0.28 0.30
16 mA 0.28 0.30
LVCMOS25
Slow 2 mA 4.04 4.21
4 mA 2.17 2.26
6 mA 1.46 1.52
8 mA 1.04 1.08
12 mA 0.65 0.68
Fast 2 mA 3.53 3.67
4 mA 1.65 1.72
6 mA 0.44 0.46
8 mA 0.20 0.21
12 mA
0
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DC and Switching Characteristics
Table 93: Output Timing Adjustments for IOB (Continued)
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Add the
Adjustment
Below
Speed Grade
-5
-4
Units
LVCMOS18
Slow 2 mA 5.03 5.24
ns
4 mA 3.08 3.21
ns
6 mA 2.39 2.49
ns
8 mA 1.83 1.90
ns
Fast 2 mA 3.98 4.15
ns
4 mA 2.04 2.13
ns
6 mA 1.09 1.14
ns
8 mA 0.72 0.75
ns
LVCMOS15
Slow 2 mA 4.49 4.68
ns
4 mA 3.81 3.97
ns
6 mA 2.99 3.11
ns
Fast 2 mA 3.25 3.38
ns
4 mA 2.59 2.70
ns
6 mA 1.47 1.53
ns
LVCMOS12
Slow 2 mA 6.36 6.63
ns
Fast 2 mA 4.26 4.44
ns
HSTL_I_18
0.33 0.34
ns
HSTL_III_18
0.53 0.55
ns
PCI33_3
0.44 0.46
ns
PCI66_3
0.44 0.46
ns
PCIX
0.82 0.85
ns
SSTL18_I
0.24 0.25
ns
SSTL2_I
–0.20 –0.20 ns
Differential Standards
LVDS_25
–0.55 –0.55 ns
BLVDS_25
0.04 0.04
ns
MINI_LVDS_25
–0.56 –0.56 ns
LVPECL_25
Input Only
ns
RSDS_25
–0.48 –0.48 ns
DIFF_HSTL_I_18
0.42 0.42
ns
DIFF_HSTL_III_18
0.53 0.55
ns
DIFF_SSTL18_I
0.40 0.40
ns
DIFF_SSTL2_I
0.44 0.44
ns
Notes:
1. The numbers in this table are tested using the methodology
presented in Table 94 and are based on the operating conditions
set forth in Table 76, Table 79, and Table 81.
2. These adjustments are used to convert output- and
three-state-path times originally specified for the LVCMOS25
standard with 12 mA drive and Fast slew rate to times that
correspond to other signal standards. Do not adjust times that
measure when outputs go into a high-impedance state.
DS312-3 (v3.4) November 9, 2006
www.xilinx.com
133
Product Specification