XC3S100E_06 Datasheet, PDF (145/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
DC and Switching Characteristics
Table 104: Switching Characteristics for the DLL (Continued)
Symbol
Phase Alignment⁽⁴⁾
CLKIN_CLKFB_PHASE
CLKOUT_PHASE_DLL
Lock Time
LOCK_DLL⁽³⁾
Delay Lines
DCM_DELAY_STEP
Description
Device
Speed Grade
-5
-4
Min
Max
Min
Max
Units
Phase offset between the CLKIN and CLKFB inputs
All
Phase offset between DLL outputs CLK0 to CLK2X
(not CLK2X180)
All others
-
±200
-
±200 ps
- ±[1% of - ±[1% of ps
CLKIN
CLKIN
period
period
+ 100]
+ 100]
- ±[1% of - ±[1% of ps
CLKIN
CLKIN
period
period
+ 200]
+ 200]
When using the DLL alone: The
5 MHz < F_CLKIN <
All
time from deassertion at the DCM’s
15 MHz
Reset input to the rising transition at
its LOCKED output. When the DCM
F_CLKIN > 15 MHz
is locked, the CLKIN and CLKFB
signals are in phase
-
5
-
5
ms
-
600
-
600
μs
Finest delay resolution
All
20
40
20
40
ps
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 76 and Table 103.
2. Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
3. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
4. Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. Example: The data sheet specifies a maximum
jitter of "±[1% of CLKIN period + 150]". Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of
10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 150 ps] = ±250ps.
DS312-3 (v3.4) November 9, 2006
www.xilinx.com
145
Product Specification