XC3S100E_06 Datasheet, PDF (20/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
R
are weakly pulled down (PULLDOWN). The designer can
control how the unused I/Os are terminated after GTS is
released by setting the Bitstream Generator (BitGen) option
UnusedPin to PULLUP, PULLDOWN, or FLOAT.
One clock cycle later (default), the Global Write Enable
(GWE) net is released allowing the RAM and registers to
change states. Once in User mode, any pull-up resistors
enabled by HSWAP revert to the user settings and HSWAP
is available as a general-purpose I/O. For more information
on PULLUP and PULLDOWN, see Pull-Up and Pull-Down
Resistors.
Behavior of Unused I/O Pins After
Configuration
By default, the Xilinx ISE development software automati-
cally configures all unused I/O pins as input pins with indi-
vidual internal pull-down resistors to GND.
This default behavior is controlled by the UnusedPin bit-
stream generator (BitGen) option, as described in Table 68.
JTAG Boundary-Scan Capability
All Spartan-3E IOBs support boundary-scan testing com-
patible with IEEE 1149.1/1532 standards. See JTAG Mode
for more information on programming via JTAG.
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DS312-2 (v3.4) November 9, 2006
Product Specification