XC3S100E_06 Datasheet, PDF (74/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
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Table 49: Serial Master Mode Connections (Continued)
Pin Name FPGA Direction
Description
DONE
Open-drain
bidirectional I/O
FPGA Configuration Done. Low during
configuration. Goes High when FPGA
successfully completes configuration.
Requires external 330 Ω pull-up resistor
to 2.5V.
PROG_B
Input
Program FPGA. Active Low. When
asserted Low for 300 ns or longer, forces
the FPGA to restart its configuration
process by clearing configuration
memory and resetting the DONE and
INIT_B pins once PROG_B returns High.
Requires external 4.7 kΩ pull-up resistor
to 2.5V. If driving externally with a 3.3V
output, use an open-drain or
open-collector driver or use a current
limiting series resistor.
During Configuration
Connects to PROM’s
chip-enable (CE) input.
Enables PROM during
configuration. Disables
PROM after configuration.
Must be High during
configuration to allow
configuration to start.
Connects to PROM’s CF pin,
allowing JTAG PROM
programming algorithm to
reprogram the FPGA.
After Configuration
Pulled High via
external pull-up.
When High, indicates
that the FPGA
successfully
configured.
Drive PROG_B Low
and release to
reprogram FPGA.
Voltage Compatibility
The PROM’s V_CCINT supply must be either 3.3V for the
serial XCFxxS Platform Flash PROMs or 1.8V for the
serial/parallel XCFxxP PROMs.
V _{The FPGA’s VCCO_2 supply input and the Platform}
Flash PROM’s V_CCO supply input must be the same volt-
age, ideally +2.5V. Both devices also support 1.8V and 3.3V
interfaces but the FPGA’s PROG_B and DONE pins require
special attention as they are powered by the FPGA’s
V_CCAUX supply, nominally 2.5V. See application note
XAPP453: The 3.3V Configuration of Spartan-3 FPGAs for
additional information.
Supported Platform Flash PROMs
Table 50 shows the smallest available Platform Flash
PROM to program one Spartan-3E FPGA. A multiple-FPGA
daisy-chain application requires a Platform Flash PROM
large enough to contain the sum of the various FPGA file
sizes.
Table 50: Number of Bits to Program a Spartan-3E
FPGA and Smallest Platform Flash PROM
Spartan-3E
FPGA
Number of
Configuration
Bits
Smallest Available
Platform Flash
XC3S100E
581,344
XCF01S
XC3S250E
1,353,728
XCF02S
XC3S500E
2,270,208
XCF04S
XC3S1200E
3,841,184
XCF04S
XC3S1600E
5,969,696
XCF08P
or 2 x XCF04S
The XC3S1600E requires an 8 Mbit PROM. Two solutions
are possible: either a single 8 Mbit XCF08P parallel/serial
PROM or two 4 Mbit XCF04S serial PROMs cascaded. The
two XCF04S PROMs use a 3.3V V_CCINT supply while the
XCF08P requires a 1.8V V_CCINT supply. If the board does
not already have a 1.8V supply available, the two cascaded
XCF04S PROM solution is recommended.
CCLK Frequency
In Master Serial mode, the FPGA’s internal oscillator gener-
ates the configuration clock frequency. The FPGA provides
this clock on its CCLK output pin, driving the PROM’s CLK
input pin. The FPGA starts configuration at its lowest fre-
quency and increases its frequency for the remainder of the
configuration process if so specified in the configuration bit-
stream. The maximum frequency is specified using the
ConfigRate bitstream generator option. Table 51 shows the
maximum ConfigRate settings, approximately equal to
MHz, for various Platform Flash devices and I/O voltages.
For the serial XCFxxS PROMs, the maximum frequency
also depends on the interface voltage.
Table 51: Maximum ConfigRate Settings for Platform
Flash
Platform Flash
Part Number
XCF01S
XCF02S
XCF04S
I/O Voltage
(VCCO_2, V_CCO)
3.3V or 2.5V
1.8V
Maximum
ConfigRate
Setting
25
12
XCF08P
XCF16P
3.3V, 2.5V, or 1.8V
25
XCF32P
74
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DS312-2 (v3.4) November 9, 2006
Product Specification