XC3S100E_06 Datasheet, PDF (139/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
DC and Switching Characteristics
Table 98: CLB Distributed RAM Switching Characteristics
Symbol
Description
Clock-to-Output Times
T_SHCKO
Time from the active edge at the CLK input to data
appearing on the distributed RAM output
Setup Times
T_DS
Setup time of data at the BX or BY input before the active
transition at the CLK input of the distributed RAM
T_AS
Setup time of the F/G address inputs before the active
transition at the CLK input of the distributed RAM
T_WS
Setup time of the write enable input before the active
transition at the CLK input of the distributed RAM
Hold Times
T_DH
Hold time of the BX, BY data inputs after the active
transition at the CLK input of the distributed RAM
T_AH, T_WH
Hold time of the F/G address inputs or the write enable
input after the active transition at the CLK input of the
distributed RAM
Clock Pulse Width
T_WPH, T_WPL Minimum High or Low pulse width at CLK input
-5
Min Max
-
2.05
0.40
-
0.46
-
0.34
-
0.13
-
0
-
0.88
-
-4
Min Max
Units
-
2.35 ns
0.46
-
ns
0.52
-
ns
0.40
-
ns
0.15
-
ns
0
-
ns
1.01
-
ns
Table 99: CLB Shift Register Switching Characteristics
Symbol
Description
Clock-to-Output Times
T_REG
Time from the active edge at the CLK input to data
appearing on the shift register output
Setup Times
T_SRLDS
Setup time of data at the BX or BY input before the active
transition at the CLK input of the shift register
Hold Times
T_SRLDH
Hold time of the BX or BY data input after the active
transition at the CLK input of the shift register
Clock Pulse Width
T_WPH, T_WPL Minimum High or Low pulse width at CLK input
-5
Min Max
-
3.62
0.41
-
0.14
-
0.88
-
-4
Min Max
Units
-
4.16 ns
0.46
-
ns
0.16
-
ns
1.01
-
ns
DS312-3 (v3.4) November 9, 2006
www.xilinx.com
139
Product Specification