XC3S100E_06 Datasheet, PDF (48/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
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Digital Clock Managers (DCMs)
Differences from the Spartan-3 Architecture
• Spartan-3E FPGAs have two, four, or eight DCMs,
depending on device size.
• The variable phase shifting feature functions differently
on Spartan-3E FPGAs than from Spartan-3 FPGAs.
• The Spartan-3E DLLs support lower input frequencies,
down to 5 MHz. Spartan-3 DLLs support down to
18 MHz.
Overview
Spartan-3E Digital Clock Managers (DCMs) provide flexi-
ble, complete control over clock frequency, phase shift and
skew. To accomplish this, the DCM employs a Delay-Locked
Loop (DLL), a fully digital control system that uses feedback
to maintain clock signal characteristics with a high degree of
precision despite normal variations in operating tempera-
ture and voltage. This section provides a fundamental
description of the DCM.
The XC3S100E FPGA has two DCMs, one at the top and
one at the bottom of the device. The XC3S250E and
XC3S500E FPGAs each include four DCMs, two at the top
and two at the bottom. The XC3S1200E and XC3S1600E
FPGAs contain eight DCMs with two on each edge (see
also Figure 45). The DCM in Spartan-3E FPGAs is sur-
rounded by CLBs within the logic array and is no longer
located at the top and bottom of a column of block RAM as
in the Spartan-3 architecture. The Digital Clock Manager is
instantiated within a design using a “DCM” primitive.
The DCM supports three major functions:
• Clock-skew Elimination: Clock skew within a system
occurs due to the different arrival times of a clock signal
at different points on the die, typically caused by the
clock signal distribution network. Clock skew increases
setup and hold time requirements and increases
clock-to-out times, all of which are undesirable in high
frequency applications. The DCM eliminates clock
skew by phase-aligning the output clock signal that it
generates with the incoming clock signal. This
mechanism effectively cancels out the clock distribution
delays.
• Frequency Synthesis: The DCM can generate a wide
range of different output clock frequencies derived from
the incoming clock signal. This is accomplished by
either multiplying and/or dividing the frequency of the
input clock signal by any of several different factors.
• Phase Shifting: The DCM provides the ability to shift
the phase of all its output clock signals with respect to
the input clock signal.
Although a single design primitive, the DCM consists of four
interrelated functional units: the Delay-Locked Loop (DLL),
the Digital Frequency Synthesizer (DFS), the Phase Shifter
(PS), and the Status Logic. Each component has its associ-
ated signals, as shown in Figure 40.
PSINCDEC
PSEN
PSCLK
DCM
Phase
Shifter
PSDONE
CLKIN
CLKFB
RST
DLL
Status
Logic
DFS
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
CLKFX
CLKFX180
LOCKED
8
STATUS [7:0]
Clock
Distribution
Delay
DS099-2_07_101205
Figure 40: DCM Functional Blocks and Associated Signals
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DS312-2 (v3.4) November 9, 2006
Product Specification