XC3S100E_06 Datasheet, PDF (46/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
R
The BCIN and BCOUT ports have associated dedicated
routing that connects adjacent multipliers within the same
column. Via the cascade connection, the BCOUT port of
one multiplier block drives the BCIN port of the multiplier
block directly above it. There is no connection to the BCIN
port of the bottom-most multiplier block in a column or a
connection from the BCOUT port of the top-most block in a
column. As an example, Figure 39 shows the multiplier cas-
cade capability within the XC3S100E FPGA, which has a
single column of multiplier, four blocks tall. For clarity, the
figure omits the register control inputs.
BCOUT
A
P
B
B_INPUT = CASCADE
BCIN
BCOUT
A
P
B
B_INPUT = CASCADE
BCIN
When using the BREG register, the cascade connection
forms a shift register structure typically used in DSP algo-
rithms such as direct-form FIR filters. When the BREG reg-
ister is omitted, the cascade structure essentially feeds the
same input value to more than one multiplier. This parallel
connection serves to create wide-input multipliers, imple-
ment transpose FIR filters, and is used in any application
that requires that several multipliers have the same input
value.
Multiplier/Block RAM Interaction
Each multiplier is located adjacent to an 18 Kbit block RAM
and shares some interconnect resources. Configuring an
18 Kbit block RAM for 36-bit wide data (512 x 36 mode) pre-
vents use of the associated dedicated multiplier.
The upper 16 bits of the ‘A’ multiplicand input are shared
with the upper 16 bits of the block RAM’s Port A Data input.
Similarly, the upper 16 bits of the ‘B’ multiplicand input are
shared with Port B’s data input. See also Figure 48,
page 64.
BCOUT
A
P
B
B_INPUT = CASCADE
BCIN
BCOUT
A
P
B
B_INPUT = DIRECT
BCIN
DS312-2_30_021505
Figure 39: Multiplier Cascade Connection
46
www.xilinx.com
DS312-2 (v3.4) November 9, 2006
Product Specification