XC3S100E_06 Datasheet, PDF (92/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
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Some x8/x16 Flash PROMs have a long setup time require-
ment on the BYTE# signal. For the FPGA to configure cor-
rectly, the PROM must be in x8 mode with BYTE# = 0 at
power-on or when the FPGA’s PROG_B pin is pulsed Low.
If required, extend the BYTE# setup time for a 3.3V PROM
using an external 680 Ω pull-down resistor on the FPGA’s
LDC2 pin or by delaying assertion of the CSI_B select input
to the FPGA.
Daisy-Chaining
DESIGN NOTE:
! ^{BPI mode daisy chain software support is available}
starting in ISE 8.2i.
Answer Record #23061
www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath
=23061
Also, in a multi-FPGA daisy-chain configuration of
more than two devices, all intermediate FPGAs
between the first and last devices must be Spartan-3E
or Virtex-5 FPGAs. The last FPGA in the chain can be
from any Xilinx FPGA family.
If the application requires multiple FPGAs with different con-
figurations, then configure the FPGAs using a daisy chain,
as shown in Figure 59. Use BPI mode (M[2:0] = <0:1:0> or
<0:1:1>) for the FPGA connected to the parallel NOR Flash
PROM and Slave Parallel mode (M[2:0] = <1:1:0>) for all
downstream FPGAs in the daisy-chain. If there are more
than two FPGAs in the chain, then last FPGA in the chain
can be from any Xilinx FPGA family. However, all interme-
diate FPGAs located in the chain between the first and last
FPGAs must from either the Spartan-3E or Virtex™-5
FPGA families.
After the master FPGA—the FPGA on the left in the dia-
gram—finishes loading its configuration data from the paral-
lel Flash PROM, the master device continues generating
addresses to the Flash PROM and asserts its CSO_B out-
put Low, enabling the next FPGA in the daisy-chain. The
next FPGA then receives parallel configuration data from
the Flash PROM. The master FPGA’s CCLK output syn-
chronizes data capture.
If HSWAP = 1, an external 4.7kΩ pull-up resistor must be
added on the CSO_B pin. If HSWAP = 0, no external pull-up
is necessary.
BPI Mode Interaction with Right and Bottom Edge
Global Clock Inputs
Some of the BPI mode configuration pins are shared with
global clock inputs along the right and bottom edges of the
device (Bank 1 and Bank 2, respectively). These pins are
not easily reclaimable for clock inputs after configuration,
especially if the FPGA application access the parallel NOR
Flash after configuration. Table 63 summarizes the shared
pins.
Table 63: Shared BPI Configuration Mode and Global
Buffer Input Pins
Device
Edge
Global Buffer
Input Pin
BPI Mode
Configuration Pin
GCLK0
RDWR_B
GCLK2
D2
GCLK3
D1
Bottom
GCLK12
D7
GCLK13
D6
GCLK14
D4
GCLK15
D3
RHCLK0
A10
RHCLK1
A9
RHCLK2
A8
RHCLK3
A7
Right
RHCLK4
A6
RHCLK5
A5
RHCLK6
A4
RHCLK7
A3
Stepping 0 Limitations when Reprogramming via
JTAG if FPGA Set for BPI Configuration
The FPGA can always be reprogrammed via the JTAG port,
regardless of the mode pin (M[2:0]) settings. However,
Stepping 0 devices have a minor limitation. If a Stepping 0
FPGA is set to configure in BPI mode and the FPGA is
attached to a parallel memory containing a valid FPGA con-
figuration file, then subsequent reconfigurations using the
JTAG port will fail. Potential workarounds include setting the
mode pins for JTAG configuration (M[2:0] = <1:0:1>) or off-
setting the initial memory location in Flash by 0x2000.
Stepping 1 and later devices fully support JTAG configura-
tion even when the FPGA mode pins are set for BPI mode.
92
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DS312-2 (v3.4) November 9, 2006
Product Specification