XC3S100E_06 Datasheet, PDF (209/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Pinout Descriptions
Table 147: FG320 Package Pinout (Continued)
Bank
3
3
3
3
XC3S500E Pin Name
IP
IP
IP/VREF_3
IO/VREF_3
XC3S1200E Pin Name
IP
IP
IP/VREF_3
IP/VREF_3
XC3S1600E Pin Name
IP
IP
IP/VREF_3
IP/VREF_3
3
VCCO_3
3
VCCO_3
3
VCCO_3
3
VCCO_3
3
VCCO_3
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
VCCAUX DONE
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DONE
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DONE
FG320
Ball
Type
R1
INPUT
U1
INPUT
J6
VREF
R4 500E: VREF(I/O)
1200E:
VREF(INPUT)
1600E:
VREF(INPUT)
F3
VCCO
H7
VCCO
K1
VCCO
L7
VCCO
N3
VCCO
A1
GND
A18
GND
B2
GND
B17
GND
C10
GND
G7
GND
G12
GND
H8
GND
H9
GND
H10
GND
H11
GND
J3
GND
J8
GND
J11
GND
K8
GND
K11
GND
K16
GND
L8
GND
L9
GND
L10
GND
L11
GND
M7
GND
M12
GND
T9
GND
U2
GND
U17
GND
V1
GND
V18
GND
V17
CONFIG
DS312-4 (v3.4) November 9, 2006
www.xilinx.com
209
Product Specification