XC3S100E_06 Datasheet, PDF (7/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Introduction and Ordering Information
Ordering Information
Spartan-3E FPGAs are available in both standard and
Pb-free packaging options for all device/package combina-
tions. All devices are available in Pb-free packages, which
adds a ‘G’ character to the ordering code. All devices are
available in either Commercial (C) or Industrial (I) tempera-
Standard Packaging
ture ranges. Both the standard –4 and faster –5 speed
grades are available for the Commercial temperature range.
However, only the –4 speed grade is available for the Indus-
trial temperature range. See Table 2 for valid device/pack-
age combinations.
Example: XC3S250E -4 FT 256 C S1 (additional code to specify Stepping 1)
Device Type
Speed Grade
Temperature Range:
C = Commercial
I = Industrial (T_J
=(T-^J4=0^{o0CoCtoto10805oo}CC))
Package Type
Number of Pins
DS312_03_111805
Pb-Free Packaging
Example: XC3S250E -4 FT G 256 C S1 (additional code to specify Stepping 1)
Device Type
Speed Grade
Package Type
Temperature Range:
C = Commercial
I = Industrial (T_J
=(T-^J4=0^{o0CoCtoto10805oo}CC))
Number of Pins
Pb-free
DS312_04_111805
Device
Speed Grade
Package Type / Number of Pins
XC3S100E –4 Standard Performance VQ(G)100 100-pin Very Thin Quad Flat Pack (VQFP)
Temperature Range (T_J)
C Commercial (0°C to 85°C)
XC3S250E –5 High Performance
CP(G)132 132-ball Chip-Scale Package (CSP)
I Industrial (–40°C to 100°C)
XC3S500E
TQ(G)144 144-pin Thin Quad Flat Pack (TQFP)
XC3S1200E
PQ(G)208 208-pin Plastic Quad Flat Pack (PQFP)
XC3S1600E
FT(G)256 256-ball Fine-Pitch Thin Ball Grid Array (FTBGA)
FG(G)320 320-ball Fine-Pitch Ball Grid Array (FBGA)
FG(G)400 400-ball Fine-Pitch Ball Grid Array (FBGA)
FG(G)484 484-ball Fine-Pitch Ball Grid Array (FBGA)
Notes:
1. The –5 speed grade is exclusively available in the Commercial temperature range.
Production Stepping
The Spartan-3E FPGA family uses production stepping to
indicate improved capabilities or enhanced features.
All devices ordered using the standard part number support
Stepping 0 functionality and performance. Later steppings
are, by definition, a functional superset of any previous step-
ping. Furthermore, configuration bitstreams generated for
any stepping are forward compatible. See Table 71 for addi-
tional details.
Xilinx ships both Stepping 0 and Stepping 1. Designs oper-
ating on the Stepping 0 devices perform similarly on a Step-
ping 1 device.
To specify only the later stepping, append an S# suffix to the
standard ordering code, where # is the stepping number, as
indicated in Table 3.
Table 3: Spartan-3E Stepping Levels
Stepping
Number Suffix Code
Status
0
None or S0
Production
1
S1
Production
DS312-1 (v3.4) November 9, 2006
www.xilinx.com
7
Product Specification