XC3S100E_06 Datasheet, PDF (68/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
R
Configuration Bitstream Image Sizes
Pin Behavior During Configuration
A specific Spartan-3E part type always requires a constant
number of configuration bits, regardless of design complex-
ity, as shown in Table 44. The configuration file size for a
multiple-FPGA daisy-chain design roughly equals the sum
of the individual file sizes.
Table 44: Number of Bits to Program a Spartan-3E
FPGA (Uncompressed Bitstreams)
Spartan-3E FPGA
Number of
Configuration Bits
XC3S100E
581,344
XC3S250E
1,353,728
XC3S500E
2,270,208
XC3S1200E
3,841,184
XC3S1600E
5,969,696
Table 45 shows how various pins behave during the FPGA
configuration process. The actual behavior depends on the
values applied to the M2, M1, and M0 mode select pins and
the HSWAP pin. The mode select pins determine which of
the I/O pins are borrowed during configuration and how they
function. In JTAG configuration mode, no user-I/O pins are
borrowed for configuration.
All user-I/O pins, input-only pins, and dual-purpose pins that
are not actively involved in the currently-select configuration
mode are high impedance (floating, three-stated, Hi-Z) dur-
ing the configuration process. These pins are indicated in
Table 45 as gray shaded table entries or cells.
The HSWAP input controls whether all user-I/O pins,
input-only pins, and dual-purpose pins have a pull-up resis-
tor to the supply rail or not. When HSWAP is Low, each pin
has an internal pull-up resistor that is active throughout con-
figuration. After configuration, pull-up and pull-down resis-
tors are available in the FPGA application as described in
Pull-Up and Pull-Down Resistors.
The yellow-shaded table entries or cells represent pins
where the pull-up resistor is always enabled during configu-
ration, regardless of the HSWAP input. The post-configura-
tion behavior of these pins is defined by Bitstream
Generator options as defined in Table 68.
Table 45: Pin Behavior during Configuration
Pin Name
SPI (Serial
Master Serial
Flash)
BPI (Parallel
NOR Flash)
JTAG
Slave
Parallel
Slave Serial
Supply/
I/O Bank
IO* (user-I/O)
IP* (input-only)
TDI
TMS
TCK
TDO
PROG_B
DONE
HSWAP
M2
TDI
TMS
TCK
TDO
PROG_B
DONE
HSWAP
0
TDI
TMS
TCK
TDO
PROG_B
DONE
HSWAP
0
TDI
TMS
TCK
TDO
PROG_B
DONE
HSWAP
0
TDI
TMS
TCK
TDO
PROG_B
DONE
HSWAP
1
TDI
TMS
TCK
TDO
PROG_B
DONE
HSWAP
1
TDI
TMS
TCK
TDO
PROG_B
DONE
HSWAP
1
-
V_CCAUX
V_CCAUX
V_CCAUX
V_CCAUX
V_CCAUX
V_CCAUX
0
2
M1
0
0
1
0
1
1
2
M0
0
1
0 = Up
1
0
1
2
1 = Down
CCLK
INIT_B
CSO_B
CCLK (I/O)
INIT_B
CCLK (I/O)
INIT_B
CSO_B
CCLK (I/O)
INIT_B
CSO_B
CCLK (I)
CCLK (I)
2
INIT_B
INIT_B
2
CSO_B
2
DOUT/BUSY
MOSI/CSI_B
D7
D6
DOUT
DOUT
MOSI
BUSY
CSI_B
D7
D6
BUSY
DOUT
2
CSI_B
2
D7
2
D6
2
D5
D5
D5
2
D4
D4
D4
2
68
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DS312-2 (v3.4) November 9, 2006
Product Specification