XC3S100E_06 Datasheet, PDF (97/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Functional Description
Table 64: Slave Parallel Mode Connections (Continued)
Pin Name FPGA Direction
Description
During Configuration
INIT_B
Open-drain
bidirectional I/O
Initialization Indicator. Active Low.
Goes Low at the start of
configuration during the Initialization
memory clearing process. Released
at the end of memory clearing, when
mode select pins are sampled. In
daisy-chain applications, this signal
requires an external 4.7 kΩ pull-up
resistor to VCCO_2.
Active during configuration. If
CRC error detected during
configuration, FPGA drives
INIT_B Low.
DONE
Open-drain
bidirectional I/O
FPGA Configuration Done. Low
during configuration. Goes High
when FPGA successfully completes
configuration. Requires external
330 Ω pull-up resistor to 2.5V.
Low indicates that the FPGA is
not yet configured.
PROG_B
Input
Program FPGA. Active Low. When
asserted Low for 300 ns or longer,
forces the FPGA to restart its
configuration process by clearing
configuration memory and resetting
the DONE and INIT_B pins once
PROG_B returns High. Requires
external 4.7 kΩ pull-up resistor to
2.5V. If driving externally with a 3.3V
output, use an open-drain or
open-collector driver or use a
current limiting series resistor.
Must be High to allow
configuration to start.
After Configuration
User I/O. If unused in the
application, drive INIT_B
High.
Pulled High via external
pull-up. When High,
indicates that the FPGA
successfully configured.
Drive PROG_B Low and
release to reprogram
FPGA.
Voltage Compatibility
V _{Most Slave Parallel interface signals are within the}
FPGA’s I/O Bank 2, supplied by the VCCO_2 supply input.
The VCCO_2 voltage can be 1.8V, 2.5V, or 3.3V to match
the requirements of the external host, ideally 2.5V. Using
1.8V or 3.3V requires additional design considerations as
the DONE and PROG_B pins are powered by the FPGA’s
2.5V V_CCAUX supply. See XAPP453: The 3.3V Configura-
tion of Spartan-3 FPGAs for additional information.
The LDC[2:0] and HDC signal are active in I/O Bank 1 but
are not used in the interface. Consequently, VCCO_1 can
be set the appropriate voltage for the application.
Daisy-Chaining
If the application requires multiple FPGAs with different con-
figurations, then configure the FPGAs using a daisy chain.
Use Slave Parallel mode (M[2:0] = <1:1:0>) for all FPGAs in
the daisy-chain. The schematic in Figure 62 is optimized for
FPGA downloading and does not support the SelectMAP
read interface. The FPGA’s RDWR_B pin must be Low dur-
ing configuration.
After the lead FPGA is filled with its configuration data, the
lead FPGA enables the next FPGA in the daisy-chain by
asserting is chip-select output, CSO_B.
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
97
Product Specification