XC3S100E_06 Datasheet, PDF (142/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

DC and Switching Characteristics
Block RAM Timing
Table 102: Block RAM Timing
Symbol
Description
Clock-to-Output Times
T_BCKO
When reading from block RAM, the delay from the
active transition at the CLK input to data appearing at
the DOUT output
Setup Times
T_BACK
Setup time for the ADDR inputs before the active
transition at the CLK input of the block RAM
T_BDCK
Setup time for data at the DIN inputs before the active
transition at the CLK input of the block RAM
T_BECK
Setup time for the EN input before the active transition
at the CLK input of the block RAM
T_BWCK
Setup time for the WE input before the active transition
at the CLK input of the block RAM
Hold Times
T_BCKA
Hold time on the ADDR inputs after the active transition
at the CLK input
T_BCKD
Hold time on the DIN inputs after the active transition at
the CLK input
T_BCKE
Hold time on the EN input after the active transition at
the CLK input
T_BCKW
Hold time on the WE input after the active transition at
the CLK input
Clock Timing
T_BPWH
High pulse width of the CLK signal
T_BPWL
Low pulse width of the CLK signal
Clock Frequency
F_BRAM
Block RAM clock frequency. RAM read output value
written back into RAM, for shift-registers and circular
buffers. Write-only or read-only performance is faster.
Speed Grade
-5
-4
Min
Max
Min
Max
-
2.45
-
2.82
0.33
-
0.38
-
0.23
-
0.23
-
0.67
-
0.77
-
1.09
-
1.26
-
0.12
-
0.14
-
0.12
-
0.13
-
0
-
0
-
0
-
0
-
1.39
-
1.59
-
1.39
-
1.59
-
0
270
0
230
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 76.
R
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
142
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DS312-3 (v3.4) November 9, 2006
Product Specification