XC3S100E_06 Datasheet, PDF (104/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Option
Option
= Bitstream Generator (BitGen) Option
= Design Attribute
Power On Reset (POR)
VCCO_2
V_CCO2T
VCCINT
V_CCINTT
VCCAUX
V_CCAUXT
PROG_B
Glitch Filter
POWER_GOOD
CCLK
1
TCK
0
M1
M2
1
ConfigRate
0
Internal
Oscillator
LOCKED
DCM in User
Application
STARTUP_WAIT=TRUE
INITIALIZATION
ENABLE
DONE
Clear internal CMOS
configuration latches
CLEARING_MEMORY
RESET WAIT
DriveDone
All DCMs
CONFIGURATION
STARTUP
DCMs_LOCKED
LCK_cycle
DONE
Enable application logic and
I/O pins
EN
DONE_cycle
ENABLE
DONE
ENABLE
Load application
data into CMOS
configuration latches
* ^{USER GTS_IN}
* ^{USER GSR_IN}
GTS
GTS_cycle
GSR
RESET
GWE
RESET WAIT
GWE_cycle
DonePipe
DONE
Force all I/Os Hi-Z
Hold all storage
elements reset
Disable write
operations to
storage elements
EN
INIT_B
JTAG_CLOCK
* ^USER_CLOCK
INTERNAL_CONFIGURATION_CLOCK
StartupClk
* These connections are available via the
STARTUP_SPARTAN3E library primitive.
CRC
ENABLE ERROR
Configuration Error
Detection
(CRC Checker)