XC3S100E_06 Datasheet, PDF(177/231 Page) Xilinx, Inc – Configurable Logic Block (CLB)

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XC3S100E_06 Datasheet, PDF (177/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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R

Pinout Descriptions

CP132 Footprint

1

2

A PROG_B TDI

3

I/O

L11P_0

4

GND

Bank 0

5

6

7

8

9

I/O

VCCAUX VCCO_0 L07P_0

GCLK10

GND

I/O

L05N_0

GCLK7

B

I/O

L01N_3

I/O

L01P_3

I/O

L11N_0

HSWAP

I/O

L10P_0

ÃÃ

I/O

L09P_0

I/O

L08P_0

I/O

L07N_0

GCLK11

INPUT

L06P_0

GCLK8

I/O

L05P_0

GCLK6

C GND

I/O

L02N_3

I/O

L02P_3

I/O

L10N_0

Â

I/O

L09N_0

I/O

L08N_0

VREF_0

GND

INPUT

L06N_0

GCLK9

I/O

L04N_0

GCLK5

I/O

D L03N_3

Â

I/O

L03P_3 VCCINT

ÃÃ

10 11

I/O

L04P_0 VCCINT

GCLK4

VCCO_0

I/O

L03N_0

Â VREF_0

12

I/O

L02N_0

Â

I/O

L02P_0

Â

GND

I/O

L03P_0

ÃÃ

I/O

L01N_0

I/O

L09N_1

LDC0

13

I/O

L01P_0

14

TDO

TCK TMS

I/O

L10N_1

LDC2

I/O

L10P_1

LDC1

I/O

L09P_1 VCCINT

HDC

E VCCO_3 INPUT

VREF_3

GND

VCCAUX VCCO_1 GND

I/O

F L05P_3

LHCLK2

I/O

G

L05N_3

LHCLK3

IRDY2

I/O

H L06N_3

LHCLK5

I/O

L04N_3

LHCLK1

GND

I/O

L07P_3

LHCLK6

I/O

L04P_3

LHCLK0

I/O

L06P_3

LHCLK4

TRDY2

I/O

L07N_3

LHCLK7

J GND VCCO_3 I/O

I/O

K VCCAUX VCCINT VREF_3

ÃÃ

L

I/O

L08P_3

I/O

L08N_3

I/O

L09P_3

M

I/O

L09N_3

I/O

L01P_2

CSO_B

GND

I/O

L03P_2

D7

GCLK12

I/O

L04P_2

D4

GCLK14

INPUT

L05P_2

RDWR_B

GCLK0

GND

I/O

N L01N_2

INIT_B

I/O

L02N_2

MOSI

CSI_B

INPUT

VREF_2

I/O

L03N_2

D6

GCLK13

I/O

L04N_2

D3

GCLK15

INPUT

L05N_2

M2

GCLK1

I/O

M1

I/O

P

L02P_2

DOUT

VCCINT VCCO_2

I/O

D5

BUSY

GND

I/O

L06P_2

D2

GCLK2

I/O

L06N_2

D1

GCLK3

VCCO_2

I/O

L07N_2

DIN

D0

I/O

L08N_2

AÂ22

I/O

L08P_2

AÂ23

I/O

L07P_2

M0

VCCAUX

I/O

L09N_2

AÂ20

I/O

L09P_2

ÂA21

GND

I/O

I/O

I/O

A0

L08N_1 L08P_1

A1

A2

INPUT

VREF_1

I/O

L06N_1

A5

RHCLK5

I/O

L04N_1

A9

RHCLK1

GND

I/O

L07N_1

A3

RHCLK7

I/O

L06P_1

A6

RHCLK4

IRDY1

I/O

L05P_1

A8

RHCLK2

I/O

VREF_1

I/O

L07P_1

A4

RHCLK6

GND

I/O

L05N_1

A7

RHCLK3

TRDY1

I/O

L04P_1

A10

RHCLK0

I/O

VCCINT L03P_1

A12

I/O

L03N_1

A11

I/O

L10N_2

VS1

A18

I/O

L10P_2

VS2

A19

I/O

VREF_2

ÃÃ

I/O

L02P_1

A14

I/O

L11N_2

CCLK

I/O

L11P_2

VS0

A17

I/O

L02N_1 VCCO_1

A13

I/O

L01P_1

A16

I/O

L01N_1

A15

DONE GND

Bank 2

Figure 82: CP132 Package Footprint (top view)

DS312-4_07_030206

16 to I/O: Unrestricted,

22 general-purpose user I/O

0 to 2

INPUT: Unrestricted,

general-purpose input pin

2

CONFIG: Dedicated

configuration pins

9

N.C.: Unconnected balls on

the XC3S100E FPGA (Â)

42 to

46

DUAL: Configuration pin, then

possible user I/O

7 to 8

VREF: User I/O or input

voltage reference for bank

16

CLK: User I/O, input, or global

buffer input

8

VCCO: Output voltage supply

for bank

4

JTAG: Dedicated JTAG port

pins

6

VCCINT: Internal core supply

voltage (+1.2V)

16 GND: Ground

4

VCCAUX: Auxiliary supply

voltage (+2.5V)

DS312-4 (v3.4) November 9, 2006

www.xilinx.com

177

Product Specification

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