XC3S100E_06 Datasheet, PDF (109/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Functional Description
Table 68: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Continued)
Option Name
Pins/Function
Affected
Values
(default)
Description
UnusedPin
Unused I/O
Pins
Pulldown Default. All unused I/O pins and input-only pins have a pull-down resistor to GND.
Pullup
All unused I/O pins and input-only pins have a pull-up resistor to the VCCO_# supply
for its associated I/O bank.
Pullnone
All unused I/O pins and input-only pins are left floating (Hi-Z, high-impedance,
three-state). Use external pull-up or pull-down resistors or logic to apply a valid signal
level.
DONE_cycle
DONE pin,
Configuration
Startup
1, 2, 3, 4, Selects the Configuration Startup phase that activates the FPGA’s DONE pin. See
5, 6 Start-Up.
GWE_cycle
All flip-flops,
LUT RAMs,
and SRL16
shift registers,
Block RAM,
Configuration
Startup
1, 2, 3, 4,
5, 6
Done
Keep
Selects the Configuration Startup phase that asserts the internal write-enable signal to
all flip-flops, LUT RAMs and shift registers (SRL16). It also enables block RAM read
and write operations. See Start-Up.
Waits for the DONE pin input to go High before asserting the internal write-enable
signal to all flip-flops, LUT RAMs and shift registers (SRL16). Block RAM read and
write operations are enabled at this time.
Retains the current GWE_cycle setting for partial reconfiguration applications.
GTS_cycle
All I/O pins,
Configuration
1, 2, 3, 4, Selects the Configuration Startup phase that releases the internal three-state control,
5, 6 holding all I/O buffers in high-impedance (Hi-Z). Output buffers actively drive, if so
configured, after this point. See Start-Up.
Done
Waits for the DONE pin input to go High before releasing the internal three-state
control, holding all I/O buffers in high-impedance (Hi-Z). Output buffers actively drive,
if so configured, after this point.
Keep Retains the current GTS_cycle setting for partial reconfiguration applications.
LCK_cycle
DCMs,
Configuration
Startup
NoWait The FPGA does not wait for selected DCMs to lock before completing configuration.
0, 1, 2, 3,
4, 5, 6
If one or more DCMs in the design have the STARTUP_WAIT attribute set to TRUE,
the FPGA waits for such DCMs to acquire their respective input clock and assert their
LOCKED output. This setting selects the Configuration Startup phase where the FPGA
waits for the DCMs to lock.
DonePin
DONE pin
Pullup
Pullnone
Internally connects a pull-up resistor between DONE pin and V_CCAUX. An external
330 Ω pull-up resistor to V_CCAUX is still recommended.
No internal pull-up resistor on DONE pin. An external 330 Ω pull-up resistor to V_CCAUX
is required.
DriveDone
DONE pin
No
When configuration completes, the DONE pin stops driving Low and relies on an
external 330 Ω pull-up resistor to V_CCAUX for a valid logic High.
Yes
When configuration completes, the DONE pin actively drives High. When using this
option, an external pull-up resistor is no longer required. Only one device in an FPGA
daisy-chain should use this setting.
DonePipe
DONE pin
No
The input path from DONE pin input back to the Startup sequencer is not pipelined.
Yes
This option adds a pipeline register stage between the DONE pin input and the Startup
sequencer. Used for high-speed daisy-chain configurations when DONE cannot rise in
a single CCLK cycle. Releases GWE and GTS signals on the first rising edge of
StartupClk after the DONE pin input goes High.
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
109
Product Specification