XC3S100E_06 Datasheet, PDF (87/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Functional Description
This addressing flexibility allows the FPGA to share the par-
allel Flash PROM with an external or embedded processor.
Depending on the specific processor architecture, the pro-
cessor boots either from the top or bottom of memory. The
FPGA is flexible and boots from the opposite end of mem-
ory from the processor. Only the processor or the FPGA
can boot at any given time. The FPGA can configure first,
holding the processor in reset or the processor can boot
first, asserting the FPGA’s PROG_B pin.
The mode select pins, M[2:0], are sampled when the
FPGA’s INIT_B output goes High and must be at defined
logic levels during this time. After configuration, when the
FPGA’s DONE output goes High, the mode pins are avail-
able as full-featured user-I/O pins.
P Similarly, the FPGA’s HSWAP pin must be Low to
enable pull-up resistors on all user-I/O pins or High to dis-
able the pull-up resistors. The HSWAP control must remain
at a constant logic level throughout FPGA configuration.
After configuration, when the FPGA’s DONE output goes
High, the HSWAP pin is available as full-featured user-I/O
pin and is powered by the VCCO_0 supply.
The RDWR_B and CSI_B must be Low throughout the con-
figuration process. After configuration, these pins also
become user I/O.
In a single-FPGA application, the FPGA’s CSO_B and
CCLK pins are not used but are actively driving during the
configuration process. The BUSY pin is not used but also
actively drives during configuration and is available as a
user I/O after configuration.
After configuration, all of the interface pins except DONE
and PROG_B are available as user I/Os. Furthermore, the
bidirectional SelectMAP configuration peripheral interface
(see Slave Parallel Mode) is available after configuration.
To continue using SelectMAP mode, set the Persist bit-
stream generator option to Yes. An external host can then
read and verify configuration data.
Table 58: Byte-Wide Peripheral Interface (BPI) Connections
Pin Name FPGA Direction
Description
During Configuration
HSWAP
P
Input
User I/O Pull-Up Control. When
Low during configuration, enables
pull-up resistors in all I/O pins to
respective I/O bank V_CCO input.
0: Pull-ups during configuration
1: No pull-ups
Drive at valid logic level
throughout configuration.
M[2:0]
A
Input
Mode Select. Selects the FPGA
configuration mode. See Design
Considerations for the HSWAP,
M[2:0], and VS[2:0] Pins.
M2 = 0, M1 = 1. Set M0 = 0 to
start at address 0, increment
addresses. Set M0 = 1 to start at
address 0xFFFFFF and
decrement addresses. Sampled
when INIT_B goes High.
CSI_B
Input
Chip Select Input. Active Low.
Must be Low throughout
configuration.
RDWR_B
LDC0
Input
Output
Read/Write Control. Active Low
write enable. Read functionality
typically only used after
configuration, if bitstream option
Persist=Yes.
PROM Chip Enable
Must be Low throughout
configuration.
Connect to PROM chip-select
input (CE#). FPGA drives this
signal Low throughout
configuration.
LDC1
Output
PROM Output Enable
Connect to the PROM
output-enable input (OE#). The
FPGA drives this signal Low
throughout configuration.
After Configuration
User I/O
User I/O
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
User I/O. If the FPGA does
not access the PROM after
configuration, drive this pin
High to deselect the
PROM. A[23:0], D[7:0],
LDC[2:1], and HDC then
become available as user
I/O.
User I/O
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
87
Product Specification