XC3S100E_06 Datasheet, PDF (132/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
DC and Switching Characteristics
Table 92: Timing for the IOB Three-State Path
Symbol
Description
Conditions
Synchronous Output Enable/Disable Times
T_IOCKHZ
T_IOCKON(2)
Time from the active transition at
the OTCLK input of the
Three-state Flip-Flop (TFF) to
when the Output pin enters the
high-impedance state
Time from the active transition at
TFF’s OTCLK input to when the
Output pin drives valid data
LVCMOS25,
12 mA output
drive, Fast slew
rate
Asynchronous Output Enable/Disable Times
T_GTS
Time from asserting the Global
Three State (GTS) input on the
STARTUP_SPARTAN3E
primitive to when the Output pin
enters the high-impedance state
LVCMOS25,
12 mA output
drive, Fast slew
rate
Set/Reset Times
T_IOSRHZ
T_IOSRON(2)
Time from asserting TFF’s SR
input to when the Output pin
enters a high-impedance state
Time from asserting TFF’s SR
input at TFF to when the Output
pin drives valid data
LVCMOS25,
12 mA output
drive, Fast slew
rate
Speed Grade
-0
-5
-4
Device Abs. Max. Max Max
Units
All
0.60
1.49 1.71 ns
All
1.09
2.70 3.10 ns
All
3.43
8.52 9.79 ns
All
0.85
2.11 2.43 ns
All
1.34
3.32 3.82 ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 94 and are based on the operating conditions set forth in
Table 76 and Table 79.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the
data Output. When this is true, add the appropriate Output adjustment from Table 93.
132
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DS312-3 (v3.4) November 9, 2006
Product Specification