XC3S100E_06 Datasheet, PDF (78/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
R
Table 52: Variant Select Codes for Various SPI Serial Flash PROMs
VS2 VS1 VS0
SPI Read
Command
Dummy
Bytes SPI Serial Flash Vendor SPI Flash Family
M25Pxx
STMicroelectronics (ST)
M25PExx/M45PExx
Atmel
AT45DB ‘D’-Series
Data Flash
AT26 / AT25
Intel
S33
Spansion (AMD, Fujitsu) S25FLxxxA
FAST READ (0x0B)
Winbond (NexFlash)
111
1
(see Figure 53)
Macronix
NX25 / W25
MX25Lxxxx
Silicon Storage
Technology (SST)
SST25LFxxxA
SST25VFxxxA
Programmable
Microelectronics Corp.
(PMC)
Pm25LVxxx
AMIC Technology
A25L
Eon Silicon Solution, Inc. EN25
M25Pxx
STMicroelectronics (ST)
M25PExx/M45PExx
Spansion (AMD, Fujitsu) S25FLxxxA
Winbond (NexFlash)
NX25 / W25
READ (0x03)
101
(see Figure 53)
Macronix
0
Silicon Storage
Technology (SST)
MX25Lxxxx
SST25LFxxxA
SST25VFxxxA
SST25VFxxx
Programmable
Microelectronics Corp.
(PMC)
Pm25LVxxx
1
1
0
READ ARRAY (0xE8)
(see Figure 54)
4
Atmel Corporation
AT45DB DataFlash
(use only ‘C’ or ‘D’
Series for Industrial
temperature range)
Others
Reserved
iMPACT
Programming
Support
Yes
Yes
Yes
Yes
W _{Table 53 shows the connections between the SPI Flash}
PROM and the FPGA’s SPI configuration interface. Each
SPI Flash PROM vendor uses slightly different signal nam-
ing. The SPI Flash PROM’s write protect and hold controls
are not used by the FPGA during configuration. However,
the HOLD pin must be High during the configuration pro-
cess. The PROM’s write protect input must be High in order
to write or program the Flash memory.
78
www.xilinx.com
DS312-2 (v3.4) November 9, 2006
Product Specification