XC3S100E_06 Datasheet, PDF (211/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Pinout Descriptions
User I/Os by Bank
Table 148 and Table 149 indicate how the available user-I/O
pins are distributed between the four I/O banks on the
FG320 package.
Table 148: User I/Os Per Bank for XC3S500E in the FG320 Package
Package
Maximum
Edge
I/O Bank
I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
58
29
14
1
6
Right
1
58
22
10
21
5
Bottom
2
58
17
13
24
4
Left
3
58
34
11
0
5
TOTAL
232
102
48
46
20
CLK
8
0⁽¹⁾
0⁽¹⁾
8
16
Notes:
1. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Table 149: User I/Os Per Bank for XC3S1200E and XC3S1600E in the FG320 Package
Package
Maximum
Edge
I/O Bank
I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
61
34
12
1
6
Right
1
63
25
12
21
5
Bottom
2
63
23
11
24
5
Left
3
63
38
12
0
5
TOTAL
250
120
47
46
21
CLK
8
0⁽¹⁾
0⁽¹⁾
8
16
Notes:
1. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
DS312-4 (v3.4) November 9, 2006
www.xilinx.com
211
Product Specification