XC3S100E_06 Datasheet, PDF (23/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Functional Description
Left-Hand SLICEM
(Logic or Distributed RAM
or Shift Register)
CLB
Right-Hand SLICEL
(Logic Only)
COUT
SLICE
X1Y1
Switch
Matrix
COUT
SHIFTOUT
SHIFTIN
SLICE
X0Y1
SLICE
X0Y0
SLICE
X1Y0
CIN
Interconnect
to Neighbors
CIN
DS099-2_05_082104
Figure 16: Arrangement of Slices within the CLB
Slice Location Designations
The Xilinx development software designates the location of
a slice according to its X and Y coordinates, starting in the
bottom left corner, as shown in Figure 14. The letter ‘X’ fol-
lowed by a number identifies columns of slices, increment-
ing from the left side of the die to the right. The letter ‘Y’
followed by a number identifies the position of each slice in
a pair as well as indicating the CLB row, incrementing from
the bottom of the die. Figure 16 shows the CLB located in
the lower left-hand corner of the die. The SLICEM always
has an even ‘X’ number, and the SLICEL always has an odd
‘X’ number.
Slice Overview
A slice includes two LUT function generators and two stor-
age elements, along with additional logic, as shown in
Figure 17.
Both SLICEM and SLICEL have the following elements in
common to provide logic, arithmetic, and ROM functions:
• Two 4-input LUT function generators, F and G
• Two storage elements
• Two wide-function multiplexers, F5MUX and FiMUX
• Carry and arithmetic logic
SRL16
RAM16
LUT4 (G)
FiMUX
Carry
Register
FiMUX
LUT4 (G) ^Carry
Register
SRL16
RAM16
LUT4 (F)
F5MUX
Carry
Register
F5MUX
Carry
LUT4 (F)
Register
Arithmetic Logic
SLICEM
Figure 17: Resources in a Slice
Arithmetic Logic
SLICEL
DS312-2_13_020905
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
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Product Specification