XC3S100E_06 Datasheet, PDF (63/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Functional Description
BUFGMUX Output
X1Y10 (Global)
X0Y9 (Left Half)
X1Y11 (Global)
X0Y8 (Left Half)
X2Y10 (Global)
X0Y7 (Left Half)
X2Y11 (Global)
X0Y6 (Left Half)
Clock Line
H
BUFGMUX Output
X1Y10 (Global)
X3Y9 (Right Half)
X1Y11 (Global)
G
X3Y8 (Right Half)
X2Y10 (Global)
F
X3Y7 (Right Half)
X2Y11 (Global)
E
X3Y6 (Right Half)
Clock Line
H
G
F
E
X1Y0 (Global)
D
X1Y0 (Global)
D
X0Y5 (Left Half)
X3Y5 (Right Half)
X1Y1 (Global)
X1Y1 (Global)
C
C
X0Y4 (Left Half)
X3Y4 (Right Half)
X2Y0 (Global)
B
X2Y0 (Global)
B
X0Y3 (Left Half)
X3Y3 (Right Half)
X2Y1 (Global)
X2Y1 (Global)
A
A
X0Y2 (Left Half)
X3Y2 (Right Half)
a. Left (TL and BL Quadrants) Half of Die
b. Right (TR and BR Quadrants) Half of Die
DS312-2_17_103105
Figure 47: Clock Sources for the Eight Clock Lines within a Clock Quadrant
The outputs of the top or bottom BUFGMUX elements con-
nect to two vertical spines, each comprising four vertical
clock lines as shown in Figure 45. At the center of the die,
these clock signals connect to the eight-line horizontal clock
spine.
Outputs of the left and right BUFGMUX elements are routed
onto the left or right horizontal spines, each comprising
eight horizontal clock lines.
Each of the eight clock signals in a clock quadrant derives
either from a global clock signal or a half clock signal. In
other words, there are up to 24 total potential clock inputs to
the FPGA, eight of which can connect to clocked elements
in a single clock quadrant. Figure 47 shows how the clock
lines in each quadrant are selected from associated BUFG-
MUX sources. For example, if quadrant clock ‘A’ in the bot-
tom left (BL) quadrant originates from BUFGMUX_X2Y1,
then the clock signal from BUFGMUX_X0Y2 is unavailable
in the bottom left quadrant. However, the top left (TL) quad-
rant clock ‘A’ can still solely use the output from either
BUFGMUX_X2Y1 or BUFGMUX_X0Y2 as the source.
To minimize the dynamic power dissipation of the clock net-
work, the Xilinx development software automatically dis-
ables all clock segments not in use.
Performance Differences between
Top/Bottom and Left-/Right-Half Global
Buffers
The top and bottom global buffers support higher clock fre-
quencies than the left- and right-half buffers. Consequently,
clocks exceeding 230 MHz must use the top or bottom glo-
bal buffers and, if required for the application, their associ-
ated DCMs. See Table 100 in Module 3.
DS312-2 (v3.4) November 9, 2006
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63
Product Specification