XC3S100E_06 Datasheet, PDF (81/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Functional Description
Table 54: Serial Peripheral Interface (SPI) Connections (Continued)
FPGA
Pin Name Direction
Description
During Configuration
After Configuration
INIT_B
Open-drain
bidirectional
I/O
Initialization Indicator. Active Low.
Goes Low at start of configuration during
Initialization memory clearing process.
Released at end of memory clearing,
when mode select pins are sampled. In
daisy-chain applications, this signal
requires an external 4.7 kΩ pull-up
resistor to VCCO_2.
Active during configuration. If
SPI Flash PROM requires > 2
ms to awake after powering on,
hold INIT_B Low until PROM is
ready. If CRC error detected
during configuration, FPGA
drives INIT_B Low.
User I/O. If unused in the
application, drive INIT_B
High.
DONE
Open-drain
bidirectional
I/O
FPGA Configuration Done. Low during
configuration. Goes High when FPGA
successfully completes configuration.
Requires external 330 Ω pull-up resistor
to 2.5V.
Low indicates that the FPGA is
not yet configured.
Pulled High via external
pull-up. When High,
indicates that the FPGA
successfully configured.
PROG_B
Input
Program FPGA. Active Low. When
asserted Low for 300 ns or longer, forces
the FPGA to restart its configuration
process by clearing configuration
memory and resetting the DONE and
INIT_B pins once PROG_B returns
High. Requires external 4.7 kΩ pull-up
resistor to 2.5V. If driving externally with
a 3.3V output, use an open-drain or
open-collector driver or use a current
limiting series resistor.
Must be High to allow
configuration to start.
Drive PROG_B Low and
release to reprogram
FPGA. Hold PROG_B to
force FPGA I/O pins into
Hi-Z, allowing direct
programming access to SPI
Flash PROM pins.
Voltage Compatibility
Available SPI Flash PROMs use a single 3.3V supply volt-
age. All of the FPGA’s SPI Flash interface signals are within
I/O Bank 2. Consequently, the FPGA’s VCCO_2 supply
voltage must also be 3.3V to match the SPI Flash PROM.
Power-On Precautions if 3.3V Supply is Last in
Sequence
Spartan-3E FPGAs have a built-in power-on reset (POR)
circuit, as shown in Figure 66. The FPGA waits for its three
power supplies — V_CCINT, V_CCAUX, and V_CCO to I/O Bank 2
(VCCO_2) — to reach their respective power-on thresholds
before beginning the configuration process.
The SPI Flash PROM is powered by the same voltage sup-
ply feeding the FPGA's VCCO_2 voltage input, typically
3.3V. SPI Flash PROMs specify that they cannot be
accessed until their V_CC supply reaches its minimum data
sheet voltage, followed by an additional delay. For some
devices, this additional delay is as little as 10 µs as shown in
Table 55. For other vendors, this delay is as much as 20 ms.
Table 55: Example Minimum Power-On to Select Times for Various SPI Flash PROMs
Vendor
SPI Flash PROM
Part Number
Data Sheet Minimum Time from V_CC min to Select = Low
Symbol
Value
Units
STMicroelectronics
M25Pxx
T_VSL
10
μs
Spansion
S25FLxxxA
t_PU
10
ms
NexFlash
NX25xx
T_VSL
10
μs
Macronix
MX25Lxxxx
t_VSL
10
μs
Silicon Storage Technology
SST25LFxx
T_PU-READ
10
μs
Programmable
Microelectronics Corporation
Pm25LVxxx
T_VCS
50
μs
Atmel Corporation
AT45DBxxxD
AT45DBxxxB
t_VCSL
30
μs
20
ms
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
81
Product Specification