XC3S100E_06 Datasheet, PDF (140/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

DC and Switching Characteristics
Clock Buffer/Multiplexer Switching Characteristics
Table 100: Clock Distribution Switching Characteristics
Description
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to
O-output delay
Global clock multiplexer (BUFGMUX) select S-input setup to
I0 and I1 inputs. Same as BUFGCE enable CE-input
Frequency of signals distributed on global buffers (all sides)
Symbol
T_GIO
T_GSI
F_BUFG
Minimum
Maximum
Speed Grade
-0
-5
-4
-
1.46
1.46
-
0.55
0.63
0
333
311
R
Units
ns
ns
MHz
140
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DS312-3 (v3.4) November 9, 2006
Product Specification