XC3S100E_06 Datasheet, PDF (77/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Functional Description
+1.2V
VCCINT
P
HSWAP
VCCO_0
SPI Mode
‘0’
M2
‘0’
M1
‘1’
M0
VCCO_2
MOSI
DIN
CSO_B
+2.5V
JTAG
TDI
TMS
TCK
TDO
Variant Select
‘1’
‘1’
‘0’
Spartan-3E
VS2
FPGA
VS1
VS0
CCLK
DOUT
INIT_B
TDI
TMS
TCK
VCCAUX
TDO
PROG_B
DONE
GND
VCCO_0
I
+3.3V
+3.3V
Atmel
AT45DB
P
DataFlash
W
‘1’
+3.3V
VCC
SI
SO
CS
WP
RESET
RDY/BUSY
SCK
GND
Power-on monitor is only required if
+3.3V (VCCO_2) supply is the last supply
in power-on sequence, after VCCINT
and VCCAUX. Must delay FPGA
configuration for > 20 ms after SPI
DataFlash reaches its minimum VCC.
Force FPGA INIT_B input OR PROG_B
input Low with an open-drain or open-
collector driver.
+3.3V
+2.5V
+2.5V
INIT_B
Power-On
Monitor
or
+3.3V
PROG_B
Recommend
open-drain
driver
PROG_B
Power-On
Monitor
Figure 54: Atmel SPI-based DataFlash Configuration Interface
DS312-2_50a_031706
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
77
Product Specification