XC3S100E_06 Datasheet, PDF (144/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
DC and Switching Characteristics
Table 104: Switching Characteristics for the DLL
Symbol
Output Frequency Ranges
CLKOUT_FREQ_CLK0
Description
Frequency for the CLK0 and
CLK180 outputs
Stepping 0
CLKOUT_FREQ_CLK90
Frequency for the CLK90 and
CLK270 outputs
Stepping 1
Stepping 0
CLKOUT_FREQ_2X
Frequency for the CLK2X and
CLK2X180 outputs
Stepping 1
Stepping 0
CLKOUT_FREQ_DV
Frequency for the CLKDV output
Stepping 1
Stepping 0
Output Clock Jitter^(2,3,4)
CLKOUT_PER_JITT_0
CLKOUT_PER_JITT_90
CLKOUT_PER_JITT_180
CLKOUT_PER_JITT_270
CLKOUT_PER_JITT_2X
Stepping 1
Period jitter at the CLK0 output
Period jitter at the CLK90 output
Period jitter at the CLK180 output
Period jitter at the CLK270 output
Period jitter at the CLK2X and CLK2X180 outputs
CLKOUT_PER_JITT_DV1
CLKOUT_PER_JITT_DV2
Period jitter at the CLKDV output when performing
integer division
Period jitter at the CLKDV output when performing
non-integer division
Duty Cycle⁽⁴⁾
CLKOUT_DUTY_CYCLE_DLL
Duty cycle variation for the CLK0, CLK90, CLK180,
CLK270, CLK2X, CLK2X180, and CLKDV outputs,
including the BUFGMUX and clock tree duty-cycle
distortion
Device
Speed Grade
-5
-4
Min
Max
Min
Max
Units
XC3S100E
5
90
5
90 MHz
XC3S250E
XC3S500E
XC3S1600E
XC3S1200E
200
200 MHz
All
275
240 MHz
XC3S100E
5
90
5
90 MHz
XC3S250E
XC3S500E
XC3S1600E
XC3S1200E
167
167 MHz
All
167
167 MHz
XC3S100E 10
180
10
180 MHz
XC3S250E
XC3S500E
XC3S1600E
XC3S1200E
333
311 MHz
All
333
311 MHz
XC3S100E 0.3125 60 0.3125 60 MHz
XC3S250E
XC3S500E
XC3S1600E
XC3S1200E
133
133 MHz
All
183
160 MHz
All
-
±100
-
±100 ps
-
±150
-
±150 ps
-
±150
-
±150 ps
-
±150
-
±150 ps
- ±[1% of - ±[1% of ps
CLKIN
CLKIN
period
period
+ 150]
+ 150]
-
±150
-
±150 ps
- ±[1% of - ±[1% of ps
CLKIN
CLKIN
period
period
+ 200]
+ 200]
All
- ±[1% of - ±[1% of ps
CLKIN
CLKIN
period
period
+ 400]
+ 400]
144
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DS312-3 (v3.4) November 9, 2006
Product Specification