XC3S100E_06 Datasheet, PDF (96/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
R
after configuration. To continue using SelectMAP mode, set
the Persist bitstream generator option to Yes. The external
host can then read and verify configuration data.
The Slave Parallel mode is also used with BPI mode to cre-
ate multi-FPGA daisy-chains. The lead FPGA is set for BPI
mode configuration; all the downstream daisy-chain FPGAs
are set for Slave Parallel configuration, as highlighted in
Figure 59.
Table 64: Slave Parallel Mode Connections
Pin Name FPGA Direction
Description
During Configuration
After Configuration
HSWAP
Input
User I/O Pull-Up Control. When
Low during configuration, enables
pull-up resistors in all I/O pins to
respective I/O bank V_CCO input.
0: Pull-ups during configuration
1: No pull-ups
Drive at valid logic level
throughout configuration.
User I/O
M[2:0]
Input
Mode Select. Selects the FPGA
configuration mode. See Design
Considerations for the HSWAP,
M[2:0], and VS[2:0] Pins.
M2 = 1, M1 = 1, M0 = 0 Sampled User I/O
when INIT_B goes High.
D[7:0]
Input
Data Input.
Byte-wide data provided by host.
FPGA captures data on rising
CCLK edge.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
BUSY
Output
Busy Indicator.
If CCLK frequency is < 50 MHz,
this pin may be ignored. When
High, indicates that the FPGA is
not ready to receive additional
configuration data. Host must
hold data an additional clock
cycle.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
CSI_B
Input
Chip Select Input. Active Low.
Must be Low throughout
configuration.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
RDWR_B
Input
Read/Write Control. Active Low
write enable.
Must be Low throughout
configuration.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
CCLK
Input
Configuration Clock. If CCLK PCB
trace is long or has multiple
connections, terminate this output to
maintain signal integrity. See CCLK
Design Considerations.
External clock.
User I/O If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
CSO_B
Output
Chip Select Output. Active Low.
Not used in single FPGA
applications. In a daisy-chain
configuration, this pin connects to
the CSI_B pin of the next FPGA in
the chain. Actively drives.
User I/O
96
www.xilinx.com
DS312-2 (v3.4) November 9, 2006
Product Specification