XC3S100E_06 Datasheet, PDF (216/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Pinout Descriptions
Table 151: FG400 Package Pinout (Continued)
Bank
XC3S1200E
XC3S1600E
Pin Name
FG400
Ball
Type
1
IO_L29P_1/HDC
E18
DUAL
1
IO_L30N_1/LDC2
C19
DUAL
1
IO_L30P_1/LDC1
C20
DUAL
1
IP
B20
INPUT
1
IP
G15 INPUT
1
IP
G18 INPUT
1
IP
H14
INPUT
1
IP
J15
INPUT
1
IP
L18
INPUT
1
IP
M20 INPUT
1
IP
N14
INPUT
1
IP
N20
INPUT
1
IP
P15
INPUT
1
IP
R16
INPUT
1
IP
R19
INPUT
1
IP/VREF_1
E19
VREF
1
IP/VREF_1
K18
VREF
1
VCCO_1
D19
VCCO
1
VCCO_1
G17
VCCO
1
VCCO_1
K15
VCCO
1
VCCO_1
K19
VCCO
1
VCCO_1
N17
VCCO
1
VCCO_1
T19
VCCO
2
IO
P8
I/O
2
IO
P13
I/O
2
IO
R9
I/O
2
IO
R13
I/O
2
IO
W15
I/O
2
IO
Y5
I/O
2
IO
Y7
I/O
2
IO
Y13
I/O
2
IO/D5
N11
DUAL
2
IO/M1
T11
DUAL
2
IO/VREF_2
Y3
VREF
2
IO/VREF_2
Y17
VREF
2
IO_L01N_2/INIT_B
V4
DUAL
2
IO_L01P_2/CSO_B
U4
DUAL
2
IO_L03N_2/MOSI/CSI_B
V5
DUAL
2
IO_L03P_2/DOUT/BUSY
U5
DUAL
2
IO_L04N_2
Y4
I/O
R
Table 151: FG400 Package Pinout (Continued)
Bank
XC3S1200E
XC3S1600E
Pin Name
FG400
Ball
Type
2
IO_L04P_2
W4
I/O
2
IO_L06N_2
T6
I/O
2
IO_L06P_2
T5
I/O
2
IO_L07N_2
U7
I/O
2
IO_L07P_2
V7
I/O
2
IO_L09N_2/VREF_2
R7
VREF
2
IO_L09P_2
T7
I/O
2
IO_L10N_2
V8
I/O
2
IO_L10P_2
W8
I/O
2
IO_L12N_2
U9
I/O
2
IO_L12P_2
V9
I/O
2
IO_L13N_2
Y8
I/O
2
IO_L13P_2
Y9
I/O
2
IO_L15N_2/D6/GCLK13
W10
DUAL/
GCLK
2
IO_L15P_2/D7/GCLK12
W9
DUAL/
GCLK
2
IO_L16N_2/D3/GCLK15
P10
DUAL/
GCLK
2
IO_L16P_2/D4/GCLK14
R10
DUAL/
GCLK
2
IO_L18N_2/D1/GCLK3
V11
DUAL/
GCLK
2
IO_L18P_2/D2/GCLK2
V10
DUAL/
GCLK
2
IO_L19N_2/DIN/D0
Y12
DUAL
2
IO_L19P_2/M0
Y11
DUAL
2
IO_L21N_2
U12
I/O
2
IO_L21P_2
V12
I/O
2
IO_L22N_2/VREF_2
W12
VREF
2
IO_L22P_2
W13
I/O
2
IO_L24N_2
U13
I/O
2
IO_L24P_2
V13
I/O
2
IO_L25N_2
P14
I/O
2
IO_L25P_2
R14
I/O
2
IO_L27N_2/A22
Y14
DUAL
2
IO_L27P_2/A23
Y15
DUAL
2
IO_L28N_2
T15
I/O
2
IO_L28P_2
U15
I/O
2
IO_L30N_2/A20
V16
DUAL
2
IO_L30P_2/A21
U16
DUAL
2
IO_L31N_2/VS1/A18
Y18
DUAL
216
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DS312-4 (v3.4) November 9, 2006
Product Specification