UPD78F0411GA-GAM-AX Datasheet, PDF (99/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 4 PORT FUNCTIONS
(2) Port registers (P1 to P4, P10 to P12, P14, P15)
These registers write the data that is output from the chip when data is output from a port.
If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is
read.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 4-17 Format of Port Register
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
P1
0
0
0
0
P13
P12
0
0
FF01H 00H (output latch) R/W
P2
0
0
P25
P24
P23
P22
P21
P20
FF02H 00H (output latch) R/W
P3
0
0
0
P34
P33
P32
P31
0
FF03H 00H (output latch) R/W
P4
0
0
0
0
0
0
0
P40
FF04H 00H (output latch) R/W
P10
0
0
0
0
0
0
P101 P100 FF0AH 00H (output latch) R/W
P11
0
0
0
0
P113 P112
0
0
FF0BH 00H (output latch) R/W
P12
0
0
0
P124^{Note 2} P123^{Note 2} P122^{Note 2} P121^{Note 2} P120
FF0CH 00H^{Note 1}(output latch) R/W^{Note 1}
P14
0
0
0
0
P143 P142 P141 P140 FF0EH 00H (output latch) R/W
P15
0
0
0
0
P153 P152 P151 P150 FF0FH 00H (output latch) R/W
Pmn
0
1
m = 1 to 4, 10 to 12, 14, 15; n = 0 to 5
Output data control (in output mode)
Input data read (in input mode)
Output 0
Input low level
Output 1
Input high level
Notes 1. P121 to P124 are read-only. These become undefined at reset.
2. When the operation mode of the pin is the clock input mode, 0 is always read.
User’s Manual U18698EJ1V0UD
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