UPD78F0411GA-GAM-AX Datasheet, PDF (224/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51, AND 52
7.3 Registers Controlling 8-Bit Timer/Event Counters 50, 51, and 52
The following five registers are used to control 8-bit timer/event counters 50, 51, and 52.
• Timer clock selection register 5n (TCL5n)
• 8-bit timer mode control register 5n (TMC5n)
• Input switch control register (ISC)
• Port mode register 3 (PM3)
• Port register 3 (P3)
(1) Timer clock selection register 5n (TCL5n)
This register sets the count clock of 8-bit timer/event counter 5n and the valid edge of the TI5n pin input.
TCL5n can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets TCL5n to 00H.
Remark n = 0 to 2
Figure 7-6. Format of Timer Clock Selection Register 50 (TCL50)
Address: FF6AH After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
TCL50
0
0
0
0
0
TCL502 TCL501 TCL500
TCL502
0
0
0
0
1
1
1
1
TCL501
0
0
1
1
0
0
1
1
TCL500
0
1
0
1
0
1
0
1
Count clock selection^Note1
fPRS =
2 MHz
fPRS =
5 MHz
Setting prohibited
fPRS =
10 MHz
f ^Note2
PRS
fPRS/2
fPRS/2²
fPRS/2⁶
fPRS/2⁸
fPRS/2¹³
2 MHz
1 MHz
500 kHz
31.25 kHz
7.81 kHz
0.24 kHz
5 MHz
2.5 MHz
1.25 MHz
78.13 kHz
19.53 kHz
0.61 kHz
10 MHz
5 MHz
2.5 MHz
156.25 kHz
39.06 kHz
1.22 kHz
Notes 1.
2.
If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
fPRS operating frequency varies depending on the supply voltage.
• VDD = 2.7 to 5.5 V: fPRS ≤ 10 MHz
• VDD = 1.8 to 2.7 V: fPRS ≤ 5 MHz
If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fRH) (XSEL
= 0), when 1.8 V ≤ VDD < 2.7 V, the setting of TCL502, TCL501, TCL500 = 0, 1, 0 (count clock: fPRS) is
prohibited.
Cautions 1. When rewriting TCL50 to other data, stop the timer operation beforehand.
2. Be sure to clear bits 3 to 7 to 0.
Remark fPRS: Peripheral hardware clock frequency
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User’s Manual U18698EJ1V0UD