UPD78F0411GA-GAM-AX Datasheet, PDF (249/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 8 8-BIT TIMERS H0, H1, AND H2
Figure 8-12. Timing of Interval Timer/Square-Wave Output Operation (1/2)
(a) Basic operation (Operation When 01H ≤ CMP0n ≤ FEH)
Count clock
Count start
8-bit timer counter Hn ^{00H 01H}
CMP0n
N 00H 01H
Clear
N
N
00H 01H 00H
Clear
TMHEn
INTTMHn
TOHn
Interval time
<1>
<2>
<2>
<3>
Level inversion,
Level inversion,
match interrupt occurrence,
match interrupt occurrence,
8-bit timer counter Hn clear
8-bit timer counter Hn clear
<1> The count operation is enabled by setting the TMHEn bit to 1. The count clock starts counting no more than
1 clock after the operation is enabled.
<2> When the value of the 8-bit timer counter Hn matches the value of the CMP0n register, the value of the timer
counter is cleared, and the level of the TOHn output is inverted. In addition, the INTTMHn signal is output at
the rising edge of the count clock.
<3> If the TMHEn bit is cleared to 0 while timer H is operating, the INTTMHn signal and TOHn output are set to
the default level. If they are already at the default level before the TMHEn bit is cleared to 0, then that level
is maintained.
Remarks 1. n = 0 to 2, however, TOH0 and TOH1 only for TOHn
2. 01H ≤ N ≤ FEH
User’s Manual U18698EJ1V0UD
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