UPD78F0411GA-GAM-AX Datasheet, PDF (175/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
Figure 6-28. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Capture Register, CR010: Compare Register) (1/2)
(a) TOC00 = 13H, PRM00 = 10H, CRC00, = 03H, TMC00 = 08H, CR010 = 0001H
TM00 register
0000H
Operable bits
(TMC003, TMC002)
00
Capture & count clear input
(TI000 pin input)
Capture register
(CR000)
Capture interrupt
(INTTM000) ^L
Compare register
(CR010)
Compare match interrupt
(INTTM010)
0000H
0001H
M
N
10
M
S
P
N
S
P
TO00 output
This is an application example where the TO00 output level is to be inverted when the count value has been
captured & cleared.
TM00 is cleared at the rising edge detection of the TI000 pin and it is captured to CR000 at the falling edge
detection of the TI000 pin.
When bit 1 (CRC001) of capture/compare control register 00 (CRC00) is set to 1, the count value of TM00 is
captured to CR000 in the phase reverse to that of the signal input to the TI000 pin, but the capture interrupt signal
(INTTM000) is not generated. However, the INTTM000 signal is generated when the valid edge of the TI010 pin
is detected. Mask the INTTM000 signal when it is not used.
User’s Manual U18698EJ1V0UD
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