UPD78F0411GA-GAM-AX Datasheet, PDF (480/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 20 RESET FUNCTION
20.1 Register for Confirming Reset Source
Many internal reset generation sources exist in the 78K0/LC3. The reset control flag register (RESF) is used to
store which source has generated the reset request.
RESF can be read by an 8-bit memory manipulation instruction.
RESET input, reset by power-on-clear (POC) circuit, and reading RESF set RESF to 00H.
Figure 20-5. Format of Reset Control Flag Register (RESF)
Address: FFACH After reset: 00H^Note R
Symbol
7
6
5
4
3
2
1
RESF
0
0
0
WDTRF
0
0
0
0
LVIRF
WDTRF
0
1
Internal reset request by watchdog timer (WDT)
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
LVIRF
0
1
Internal reset request by low-voltage detector (LVI)
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
Note The value after reset varies depending on the reset source.
Caution Do not read data by a 1-bit memory manipulation instruction.
The status of RESF when a reset request is generated is shown in Table 20-3.
Table 20-3. RESF Status When Reset Request Is Generated
Reset Source RESET Input
Flag
WDTRF
Cleared (0)
LVIRF
Reset by POC Reset by WDT Reset by LVI
Cleared (0)
Set (1)
Held
Held
Set (1)
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User’s Manual U18698EJ1V0UD