UPD78F0411GA-GAM-AX Datasheet, PDF (209/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
Figure 6-54. Configuration Diagram of External 24-bit Event Counter
Block of external 24-bit event counter
fPRS
fPRS/2
fPRS/2²
fPRS/2⁴
fPRS/2⁸
fSUB
TI000 valid edge
TM52 output
16-bit timer/event counter 00
<Block of interval timer operation>
Internal bus
Count clock
16-bit counter (TM00)
3
Operation enable bit
TMC003, TMC002
CR000 register
PRM002 PRM001 PRM000
INTTM000
8-bit timer/event counter 52
<Block of external event timer operation>
ISC2
TI52
D
Q
CK
fPRS
fPRS/2
fPRS/2⁴
fPRS/2⁶
fPRS/2⁸
fPRS/2¹²
Count clock
Internal bus
8-bit counter (TM52)
3 ^{Operation enable bit}
TCE52
CR52 register
from TMH2 internal signal output
(input enable signal of TI52 pin)
TCL522 TCL512 TCL502
to TM00
INTTM52
Block of TI52 input enable control
fPRS
fPRS/2
fPRS/2²
fPRS/2⁴
fPRS/2⁶
fPRS/2¹⁰
fPRS/2¹²
8-bit timer H2
<Block of PWM output operation>
TOLEV2 TOEN2
Count clock
8-bit counter H2
Operation enable bit
TMHE2
3
2
Selector
CKS22 CKS21 CKS20
TMMD21 TMMD20 ^{CMP12 register CMP02 register}
output Invert
controller level
to TM00
(TMH2 output:
input enable
signal of TI52 pin)
INTTMH2
User’s Manual U18698EJ1V0UD
207