UPD78F0411GA-GAM-AX Datasheet, PDF (157/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
Figure 6-9. Format of Prescaler Mode Register 00 (PRM00)
Address: FFBBH After reset: 00H R/W
Symbol
7
6
5
PRM00
ES101
ES100
ES001
4
ES000
3
2
1
0
0
PRM002 PRM001 PRM000
ES101
0
0
1
1
ES100
0
1
0
1
TI010 pin valid edge selection
Falling edge
Rising edge
Setting prohibited
Both falling and rising edges
ES001
0
0
1
1
ES000
0
1
0
1
TI000 pin valid edge selection
Falling edge
Rising edge
Setting prohibited
Both falling and rising edges
PRM002
0
0
0
0
1
1
1
1
PRM001
0
0
1
1
0
0
1
1
PRM000
0
1
0
1
0
1
0
1
Count clock selection^Note1
f ^Note2
PRS
fPRS = 2 MHz fPRS = 5 MHz
2 MHz
5 MHz
fPRS/2
fPRS/2²
fPRS/2⁴
fPRS/2⁸
1 MHz
500 kHz
1.25 MHz
7.81 kHz
2.5 MHz
1.25 MHz
2.5 MHz
19.53 kHz
fSUB
TI000 valid edge^Note3
32.768 kHz
TM52 output
fPRS = 10 MHz
10 MHz
5 MHz
2.5 MHz
625 kHz
39.06 kHz
Notes 1.
2.
3.
If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
fPRS operating frequency varies depending on the supply voltage.
• VDD = 2.7 to 5.5 V: fPRS ≤ 10 MHz
• VDD = 1.8 to 2.7 V: fPRS ≤ 5 MHz
If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fRH) (XSEL
= 0), when 1.8 V ≤ VDD < 2.7 V, the setting of PRM002 = PRM001 = PRM000 = 0 (count clock: fPRS) is
prohibited.
The external clock from the TI000 pin requires a pulse longer than twice the cycle of the peripheral
hardware clock (fPRS).
Caution Do not select the valid edge of TI000 as the count clock during the pulse width measurement.
Remarks 1. 8-bit timer/event counter 52 (TM52) output can be selected as the TM00 count clock by setting
PRM002, PRM001, PRM000 = 1, 1, 1. Any frequency can be set as the 16-bit timer (TM00) count
clock, depending on the TM52 count clock and compare register setting values.
2. fPRS: Peripheral hardware clock frequency
fSUB: Subsystem clock frequency
User’s Manual U18698EJ1V0UD
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