UPD78F0411GA-GAM-AX Datasheet, PDF (372/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 14 SERIAL INTERFACE UART6
14.4.4 Calculation of baud rate
(1) Baud rate calculation expression
The baud rate can be calculated by the following expression.
•
fXCLK6
Baud rate =
[bps]
2×k
fXCLK6: Frequency of base clock selected by TPS63 to TPS60 bits of CKSR6 register
k:
Value set by MDL67 to MDL60 bits of BRGC6 register (k = 4, 5, 6, ..., 255)
TPS63
0
0
0
0
0
0
0
0
1
1
1
1
Table 14-4. Set Value of TPS63 to TPS60
TPS62
TPS61
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
Other than above
TPS60
0
1
0
1
0
1
0
1
0
1
0
1
Base Clock (fXCLK6) Selection^{Note 1}
fPRS =
2 MHz
fPRS =
5 MHz
fPRS =
8 MHz
fPRS =
10 MHz
f ^{Note 2}
PRS
2 MHz
5 MHz
8 MHz
10 MHz
fPRS/2 1 MHz
2.5 MHz 4 MHz
5 MHz
fPRS/2² 500 kHz 1.25 MHz 2 MHz
2.5 MHz
fPRS/2³ 250 kHz 625 kHz 1 MHz
1.25 MHz
fPRS/2⁴ 125 kHz 312.5 kHz 500 kHz 625 kHz
fPRS/2⁵ 62.5 kHz 156.25 kHz 250 kHz 312.5 kHz
fPRS/2⁶ 31.25 kHz 78.13 kHz 125 kHz 156.25 kHz
fPRS/2⁷ 15.625 kHz 39.06 kHz 62.5 kHz 78.13 kHz
fPRS/2⁸ 7.813 kHz 19.53 kHz 31.25 kHz 39.06 kHz
fPRS/2⁹ 3.906 kHz 9.77 kHz 15.625 kHz 19.53 kHz
fPRS/2¹⁰ 1.953 kHz 4.88 kHz 7.813 kHz 9.77 kHz
TM50 output^{Note 3}
Setting prohibited
Notes 1.
2.
3.
If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
fPRS operating frequency varies depending on the supply voltage.
• VDD = 2.7 to 5.5 V: fPRS ≤ 10 MHz
• VDD = 1.8 to 2.7 V: fPRS ≤ 5 MHz
If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fRH) (XSEL
= 0), when 1.8 V ≤ VDD < 2.7 V, the setting of TPS63 = TPS62 = TPS61 = TPS60 = 0 (base clock: fPRS)
is prohibited.
When selecting the TM50 output as the base clock, Start the operation of 8-bit timer/event counter 50
first and then enable the timer F/F inversion operation (TMC501 = 1).
370
User’s Manual U18698EJ1V0UD