UPD78F0411GA-GAM-AX Datasheet, PDF (485/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 21 POWER-ON-CLEAR CIRCUIT
21.4 Cautions for Power-on-Clear Circuit
In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection
voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from
release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
<Action>
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
software counter that uses a timer, and then initialize the ports.
Figure 21-3. Example of Software Processing After Reset Release (1/2)
• If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage
Reset
Initialization
processing <1>
Power-on-clear
; Check the reset source^{Note 2}
Initialize the port.
Setting 8-bit timer H1
(to measure 50 ms)
; fPRS = Internal high-speed oscillation clock (8.4 MHz (MAX.)) (default)
Source: fPRS (8.4 MHz (MAX.))/2¹²,
where comparison value = 102: ≅ 50 ms
Timer starts (TMHE1 = 1).
Note 1
Clearing WDT
No
50 ms has passed?
(TMIFH1 = 1?)
Yes
Initialization
processing <2>
; Setting of division ratio of system clock,
such as setting of timer or A/D converter
Notes 1. If reset is generated again during this period, initialization processing <2> is not started.
2. A flowchart is shown on the next page.
User’s Manual U18698EJ1V0UD
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