UPD78F0411GA-GAM-AX Datasheet, PDF (256/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 8 8-BIT TIMERS H0, H1, AND H2
Figure 8-14. Operation Timing in PWM Output Mode (4/4)
(e) Operation by changing CMP1n (CMP1n = 02H → 03H, CMP0n = A5H)
Count clock
8-bit timer
counter Hn
00H
01H 02H
80H
A5H 00H 01H 02H 03H
A5H 00H 01H 02H 03H
A5H 00H
CMP0n
A5H
CMP1n
TMHEn
02H
<2>
02H (03H)
03H
<2>’
INTTMHn
TOHn
(TOLEVn = 0)
<1>
<3>
<4>
<5>
<6>
<1> The count operation is enabled by setting TMHEn = 1. Start 8-bit timer counter Hn by masking one count
clock to count up. At this time, PWM output outputs an inactive level.
<2> The CMP1n register value can be changed during timer counter operation. This operation is asynchronous
to the count clock.
<3> When the values of 8-bit timer counter Hn and the CMP0n register match, the value of 8-bit timer counter Hn
is cleared, an active level is output, and the INTTMHn signal is output.
<4> If the CMP1n register value is changed, the value is latched and not transferred to the register. When the
values of the 8-bit timer counter Hn and the CMP1n register before the change match, the value is
transferred to the CMP1n register and the CMP1n register value is changed (<2>’).
However, three count clocks or more are required from when the CMP1n register value is changed to when
the value is transferred to the register. If a match signal is generated within three count clocks, the changed
value cannot be transferred to the register.
<5> When the values of 8-bit timer counter Hn and the CMP1n register after the change match, an inactive level
is output. 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated.
<6> Clearing the TMHEn bit to 0 during timer Hn operation sets the INTTMHn signal to the default and PWM
output to an inactive level.
Remark n = 0 to 2, however, TOH0 and TOH1 only for TOHn
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User’s Manual U18698EJ1V0UD