UPD78F0411GA-GAM-AX Datasheet, PDF (234/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51, AND 52
7.5 Cautions for 8-Bit Timer/Event Counters 50, 51, and 52
(1) Timer start error
An error of up to one clock may occur in the time required for a match signal to be generated after timer start.
This is because 8-bit timer counters 50, 51, and 52 (TM50, TM51, and TM52) are started asynchronously to the
count clock.
Figure 7-16. 8-Bit Timer Counter 5n Start Timing
Count clock
TM5n count value
00H
01H
02H
03H
04H
Timer start
Remark n = 0 to 2
(2) Cautions for 16-bit timer/event counter 00 count up during external 24-bit event counter operation
16-bit timer/event counter 00 has an internal synchronization circuit to eliminate noise when starting operation,
and the first clock immediately after operation start is not counted.
When using the counter as a 24-bit counter, by setting 16-bit timer/event counter 00 and 8-bit timer/event counter
52 as the higher and lower timer and connecting them in cascade, the interrupt request flag of 8-bit timer/event
counter 52 which is the lower timer must be checked as described below, in order to accurately read the 24-bit
count values.
- If TMIF52 = 1 when TM52 and TM00 are read:
The actual TM00 count value is “read value of TM00 + 1”.
- If TMIF52 = 0 when TM52 and TM00 are read:
The read value is the correct value.
This phenomenon of 16-bit timer/event counter 00 occurs only when operation is started. A count delay will not
occur when 16-bit timer/event counter 00 overflows and the count is restarted from 0000H, since synchronization
has already been implemented.
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User’s Manual U18698EJ1V0UD