UPD78F0411GA-GAM-AX Datasheet, PDF (462/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 19 STANDBY FUNCTION
Table 19-1. Operating Statuses in HALT Mode (1/2)
HALT Mode Setting
When HALT Instruction Is Executed While CPU Is Operating on Main System Clock
Item
When CPU Is Operating on
Internal High-Speed
Oscillation Clock (fRH)
When CPU Is Operating on
X1 Clock (fX)
When CPU Is Operating on
External Main System Clock
(fEXCLK)
System clock
Clock supply to the CPU is stopped
Main system clock fRH
Operation continues (cannot
be stopped)
Status before HALT mode was set is retained
fX
Status before HALT mode
Operation continues (cannot Status before HALT mode
was set is retained
be stopped)
was set is retained
fEXCLK Operates or stops by external clock input
Operation continues (cannot
be stopped)
Subsystem clock fXT
Status before HALT mode was set is retained
fRL
Status before HALT mode was set is retained
CPU
Operation stopped
Flash memory
RAM
Status before HALT mode was set is retained
Port (latch)
16-bit timer/event counter 00 Operable
8-bit timer/event
50
counter
51
52
8-bit timer
H0
H1
H2
Real-time counter
Watchdog timer
Operable. Clock supply to watchdog timer stops when “internal low-speed oscillator can be
stopped by software” is set by option byte.
Buzzer output
Operable
10-bit successive approximation
type A/D converter^Note
Serial interface UART0
UART6
LCD controller/driver
Manchester code generator
Remote controller receiver
Power-on-clear function
Low-voltage detection function
External interrupt
Note μPD78F041x only.
Remark
fRH:
fX:
fEXCLK:
fXT:
fRL:
Internal high-speed oscillation clock
X1 clock
External main system clock
XT1 clock
Internal low-speed oscillation clock
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User’s Manual U18698EJ1V0UD