UPD78F0411GA-GAM-AX Datasheet, PDF (368/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 14 SERIAL INTERFACE UART6
(g) Noise filter of receive data
The RxD6 signal is sampled with the base clock output by the prescaler block.
If two sampled values are the same, the output of the match detector changes, and the data is sampled as
input data.
Because the circuit is configured as shown in Figure 14-23, the internal processing of the reception operation
is delayed by two clocks from the external signal status.
Base clock
Figure 14-23. Noise Filter Circuit
RXD6
In
Q
Internal signal A
Match detector
In
Q
LD_EN
Internal signal B
(h) SBF transmission
When the device is use in LIN communication operation, the SBF (Synchronous Break Field) transmission
control function is used for transmission. For the transmission operation of LIN, see Figure 14-1 LIN
Transmission Operation.
When bit 7 (POWER6) of asynchronous serial interface mode register 6 (ASIM6) is set to 1, the TXD6 pin
outputs high level. Next, when bit 6 (TXE6) of ASIM6 is set to 1, the transmission enabled status is entered,
and SBF transmission is started by setting bit 5 (SBTT6) of asynchronous serial interface control register 6
(ASICL6) to 1.
Thereafter, a low level of bits 13 to 20 (set by bits 4 to 2 (SBL62 to SBL60) of ASICL6) is output. Following
the end of SBF transmission, the transmission completion interrupt request (INTST6) is generated and
SBTT6 is automatically cleared. Thereafter, the normal transmission mode is restored.
Transmission is suspended until the data to be transmitted next is written to transmit buffer register 6 (TXB6),
or until SBTT6 is set to 1.
Figure 14-24. SBF Transmission
TXD6
1 2 3 4 5 6 7 8 9 10 11 12 13 Stop
INTST6
SBTT6
Remark
TXD6: TXD6 pin (output)
INTST6: Transmission completion interrupt request
SBTT6: Bit 5 of asynchronous serial interface control register 6 (ASICL6)
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User’s Manual U18698EJ1V0UD