UPD78F0411GA-GAM-AX Datasheet, PDF (117/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 5 CLOCK GENERATOR
(6) Main clock mode register (MCM)
This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware
clock.
MCM can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 5-6. Format of Main Clock Mode Register (MCM)
Address: FFA1H After reset: 00H R/W^Note
Symbol
7
6
5
4
MCM
0
0
0
0
3
<2>
<1>
0
XSEL
MCS
<0>
MCM0
XSEL
0
0
1
1
MCM0
0
1
0
1
Selection of clock supplied to main system clock and peripheral hardware
Main system clock (fXP)
Peripheral hardware clock (fPRS)
Internal high-speed oscillation clock
(fRH)
Internal high-speed oscillation clock
(fRH)
High-speed system clock (fXH)
High-speed system clock (fXH)
MCS
0
1
Main system clock status
Operates with internal high-speed oscillation clock
Operates with high-speed system clock
Note Bit 1 is read-only.
Cautions 1. XSEL can be changed only once after a reset release.
2. A clock other than fPRS is supplied to the following peripheral functions
regardless of the setting of XSEL and MCM0.
• Watchdog timer (operates with internal low-speed oscillation clock)
• When “fRL”, “fRL/2⁷”, or “fRL/2⁹” is selected as the count clock for 8-bit timer H1
(operates with internal low-speed oscillation clock)
• When “fRL/2³â€ is selected as the LCD source clock for LCD controller/driver
(operates with internal low-speed oscillation clock)
• Peripheral hardware selects the external clock as the clock source
(Except when the external count clock of TM00 is selected (TI000 pin valid
edge))
User’s Manual U18698EJ1V0UD
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