UPD78F0411GA-GAM-AX Datasheet, PDF (208/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.4.9 External 24-bit event counter operation
16-bit timer/event counter 00 can be operated to function as an external 24-bit event counter, by connecting 16-bit
timer/event counter 00 and 8-bit timer/event counter 52 in cascade, and using the external event counter function of 8-
bit timer/event counter 52.
It operates as an external 24-bit event counter, by counting the number of external clock pulses input to the TI52
pin via 8-bit timer counter 52 (TM52), and counting the signal which has been output upon a match between the TM52
count value and 8-bit timer compare register 52 (CR52 = FFH^Note) via 16-bit timer counter 00 (TM00).
When using 16-bit timer/event counter 00 as an external 24-bit event counter, external event input enable can be
controlled via 8-bit timer counter H2 output.
The valid edge of the input to the TI52 pin can be specified by timer clock selection register 52 (TCL52) of 8-bit
timer counter 52 (TM52). Also, input enable for TM52 external event input can be controlled via 8-bit timer counter H2
output, by setting bit 2 (ISC2) of the input switch control register (ISC) to “1”.
Count operation using 8-bit timer 52 output as the count clock is started, by setting bits 2, 1, and 0 (PRM002,
PRM001, and PRM000) of prescaler mode register 00 (PRM00) of 16-bit timer/event counter 00 to “1”, “1”, and “1”
(TM52 output is selected as a count clock), and bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control
register 00 (TMC00) to “1” and “1” (count clear & start mode entered upon a match between TM00 and CR000).
TM00 is cleared to “0” and an interrupt request signal (INTTM000) is generated upon a match between the TM00
count value and 16-bit timer compare register 000 (CR000) value.
Subsequently, INTTM000 is generated upon every match between the TM00 and CR000 values.
Note When operating 16-bit timer/event counter 00 as an external 24-bit event counter, the 8-bit timer compare
register 52 (CR52) value must be set to FFH. Also, the TM52 interrupt request signal (INTTM52) must be
masked (TMMK52 = 1).
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User’s Manual U18698EJ1V0UD