UPD78F0411GA-GAM-AX Datasheet, PDF (284/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 10 WATCHDOG TIMER
10.3 Register Controlling Watchdog Timer
The watchdog timer is controlled by the watchdog timer enable register (WDTE).
(1) Watchdog timer enable register (WDTE)
Writing ACH to WDTE clears the watchdog timer counter and starts counting again.
This register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 9AH or 1AH^Note.
Figure 10-2. Format of Watchdog Timer Enable Register (WDTE)
Address: FF99H After reset: 9AH/1AH^Note R/W
Symbol
7
6
5
4
3
2
1
0
WDTE
Note The WDTE reset value differs depending on the WDTON setting value of the option byte (0080H). To
operate watchdog timer, set WDTON to 1.
WDTON Setting Value
0 (watchdog timer count operation disabled)
1 (watchdog timer count operation enabled)
WDTE Reset Value
1AH
9AH
Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated. If the
source clock to the watchdog timer is stopped, however, an internal reset signal is
generated when the source clock to the watchdog timer resumes operation.
2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset signal
is generated. If the source clock to the watchdog timer is stopped, however, an internal
reset signal is generated when the source clock to the watchdog timer resumes operation.
3. The value read from WDTE is 9AH/1AH (this differs from the written value (ACH)).
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User’s Manual U18698EJ1V0UD