UPD78F0411GA-GAM-AX Datasheet, PDF (170/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.4.4 Operation in clear & start mode entered by TI000 pin valid edge input
When bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 10 (clear &
start mode entered by the TI000 pin valid edge input) and the count clock (set by PRM00) is supplied to the
timer/event counter, TM00 starts counting up. When the valid edge of the TI000 pin is detected during the counting
operation, TM00 is cleared to 0000H and starts counting up again. If the valid edge of the TI000 pin is not detected,
TM00 overflows and continues counting.
The valid edge of the TI000 pin is a cause to clear TM00. Starting the counter is not controlled immediately after
the start of the operation.
CR000 and CR010 are used as compare registers and capture registers.
(a) When CR000 and CR010 are used as compare registers
Signals INTTM000 and INTTM010 are generated when the value of TM00 matches the value of CR000 and
CR010.
(b) When CR000 and CR010 are used as capture registers
The count value of TM00 is captured to CR000 and the INTTM000 signal is generated when the valid edge is
input to the TI010 pin (or when the phase reverse to that of the valid edge is input to the TI000 pin).
When the valid edge is input to the TI000 pin, the count value of TM00 is captured to CR010 and the
INTTM010 signal is generated. As soon as the count value has been captured, the counter is cleared to
0000H.
Caution Do not set the count clock as the valid edge of the TI000 pin (PRM002, PRM001, and PRM000 =
110). When PRM002, PRM001, and PRM000 = 110, TM00 is cleared.
Remarks 1. For the setting of the I/O pins, see 6.3 (6) Port mode register 3 (PM3).
2. For how to enable the INTTM000 signal interrupt, see CHAPTER 17 INTERRUPT FUNCTIONS.
(1) Operation in clear & start mode entered by TI000 pin valid edge input
(CR000: compare register, CR010: compare register)
Figure 6-23. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Compare Register, CR010: Compare Register)
TI000 pin
Count clock
Edge
detection
Operable bits
TMC003, TMC002
Clear
Timer counter
(TM00)
Match signal
Compare register
(CR000)
Match signal
Compare register
(CR010)
Output
controller
Interrupt signal
(INTTM000)
TO00
output
TO00 pin
Interrupt signal
(INTTM010)
168
User’s Manual U18698EJ1V0UD