UPD78F0411GA-GAM-AX Datasheet, PDF (287/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 10 WATCHDOG TIMER
10.4.3 Setting window open period of watchdog timer
Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option
byte (0080H). The outline of the window is as follows.
• If “ACH” is written to WDTE during the window open period, the watchdog timer is cleared and starts counting
again.
• Even if “ACH” is written to WDTE during the window close period, an abnormality is detected and an internal
reset signal is generated.
Example: If the window open period is 25%
Counting
starts
Window close period (75%)
Overflow
time
Window open
period (25%)
Internal reset signal is generated
if ACH is written to WDTE.
Counting starts again when
ACH is written to WDTE.
Caution The first writing to WDTE after a reset release clears the watchdog timer, if it is made before the
overflow time regardless of the timing of the writing, and the watchdog timer starts counting
again.
The window open period to be set is as follows.
Table 10-4. Setting Window Open Period of Watchdog Timer
WINDOW1 WINDOW0
Window Open Period of Watchdog Timer
0
0
25%
0
1
50%
1
0
75%
1
1
100%
Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0
is prohibited.
2. The watchdog timer continues its operation during self-programming and EEPROM
emulation of the flash memory. During processing, the interrupt acknowledge time
is delayed. Set the overflow time and window size taking this delay into
consideration.
User’s Manual U18698EJ1V0UD
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