UPD78F0411GA-GAM-AX Datasheet, PDF (248/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 8 8-BIT TIMERS H0, H1, AND H2
8.4 Operation of 8-Bit Timers H0, H1 and H2
8.4.1 Operation as interval timer/square-wave output
When the 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn)
is generated and the 8-bit timer counter Hn is cleared to 00H.
Compare register 1n (CMP1n) is not used in interval timer mode. Since a match of the 8-bit timer counter Hn and
the CMP1n register is not detected even if the CMP1n register is set, timer output is not affected.
By setting bit 0 (TOENn) of timer H mode register n (TMHMDn) to 1, a square wave of any frequency (duty = 50%)
is output from TOHn.
The timer output of TMH2 can only be used as an external event input enable signal of TM52. Note, no pins for
external output are available.
Setting
<1> Set each register.
Figure 8-11. Register Setting During Interval Timer/Square-Wave Output Operation
(i) Setting timer H mode register n (TMHMDn)
TMHEn
TMHMDn
0
CKSn2 CKSn1
0/1
0/1
CKSn0 TMMDn1 TMMDn0 TOLEVn TOENn
0/1
0
0
0/1
0/1
Timer output setting
Default setting of timer output level
Interval timer mode setting
Count clock (fCNT) selection
Count operation stopped
(ii) CMP0n register setting
The interval time is as follows if N is set as a comparison value.
• Interval time = (N +1)/fCNT
<2> Count operation starts when TMHEn = 1.
<3> When the values of the 8-bit timer counter Hn and the CMP0n register match, the INTTMHn signal is
generated and the 8-bit timer counter Hn is cleared to 00H.
<4> Subsequently, the INTTMHn signal is generated at the same interval. To stop the count operation, clear
TMHEn to 0.
Remarks 1. For the setting of the output pin, see 8.3 (3) Port mode register 3 (PM3).
2. For how to enable the INTTMHn signal interrupt, see CHAPTER 17 INTERRUPT FUNCTIONS.
3. n = 0 to 2, however, TOH0 and TOH1 only for TOHn
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User’s Manual U18698EJ1V0UD