UPD78F0411GA-GAM-AX Datasheet, PDF (479/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 20 RESET FUNCTION
Table 20-2. Hardware Statuses After Reset Acknowledgment (3/3)
Hardware
Status After Reset
Acknowledgment^{Note 1}
Serial interface UART6 Receive buffer register 6 (RXB6)
FFH
Transmit buffer register 6 (TXB6)
FFH
Asynchronous serial interface operation mode register 6 (ASIM6)
01H
Asynchronous serial interface reception error status register 6 (ASIS6)
00H
Asynchronous serial interface transmission status register 6 (ASIF6)
00H
Clock selection register 6 (CKSR6)
00H
Baud rate generator control register 6 (BRGC6)
FFH
Asynchronous serial interface control register 6 (ASICL6)
16H
Input switch control register (ISC)
00H
LCD controller/driver
LCD mode register (LCDMD)
00H
LCD display mode register (LCDM)
00H
LCD clock control register 0 (LCDC0)
00H
Manchester code
Transmit buffer register (MC0TX)
FFH
generator
Transmit bit count specification register (MC0BIT)
07H
Control register 0 (MC0CTL0)
10H
Control register 1 (MC0CTL1)
00H
Control register 2 (MC0CTL2)
1FH
Status register (MC0STR)
00H
Key interrupt
Reset function
Low-voltage detector
Key return mode register (KRM)
Reset control flag register (RESF)
Low-voltage detection register (LVIM)
Low-voltage detection level selection register (LVIS)
00H
00H^{Note 2}
00H^{Note 2}
00H^{Note 2}
Interrupt
Request flag registers 0L, 0H, 1L, 1H (IF0L, IF0H, IF1L, IF1H)
00H
Mask flag registers 0L, 0H, 1L, 1H (MK0L, MK0H, MK1L, MK1H)
FFH
Priority specification flag registers 0L, 0H, 1L, 1H (PR0L, PR0H, PR1L,
FFH
PR1H)
External interrupt rising edge enable register (EGP)
00H
External interrupt falling edge enable register (EGN)
00H
Notes 1.
2.
During reset signal generation or oscillation stabilization time wait, only the PC contents among the
hardware statuses become undefined. All other hardware statuses remain unchanged after reset.
These values vary depending on the reset source.
Register
RESF
LVIM
LVIS
Reset Source RESET Input
WDTRF bit
LVIRF bit
Cleared (0)
Cleared (00H)
Reset by POC Reset by WDT Reset by LVI
Cleared (0)
Cleared (00H)
Set (1)
Held
Cleared (00H)
Held
Set (1)
Held
User’s Manual U18698EJ1V0UD
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