UPD78F0411GA-GAM-AX Datasheet, PDF (471/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 19 STANDBY FUNCTION
(b) Release by reset signal generation
When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 19-7. STOP Mode Release by Reset
(1) When high-speed system clock is used as CPU clock
STOP
instruction
Reset signal
Status of CPU
High-speed
system clock
(X1 oscillation)
Normal operation
(high-speed
system clock)
STOP mode
Reset
Reset ^processing
period (11 to 47 μs)
Normal operation
(internal high-speed
oscillation clock)
Oscillates
Oscillation Oscillation
Oscillation stopped stopped stopped
Oscillates
Oscillation stabilization time
Starting X1 oscillation is ^{(211/fX to 216/fX)}
specified by software.
(2) When internal high-speed oscillation clock is used as CPU clock
STOP
instruction
Reset signal
Normal operation
(internal high-speed
Status of CPU _{oscillation clock)}
STOP mode
Reset
Reset processing
period (11 to 47 μs)
Normal operation
(internal high-speed
oscillation clock)
Internal high-speed
oscillation clock
Oscillates
Oscillation
Oscillation stopped stopped
Oscillates
Wait for oscillation
accuracy stabilization
(86 to 361 μs)
Remark fX: X1 clock oscillation frequency
Table 19-4. Operation in Response to Interrupt Request in STOP Mode
Release Source
Maskable interrupt
request
Reset
×: don’t care
MK×× PR××
IE
0
0
0
0
0
1
0
1
0
0
1
×
0
1
1
1
×
×
−
−
×
ISP
Operation
× Next address
instruction execution
× Interrupt servicing
execution
1 Next address
0
instruction execution
1 Interrupt servicing
execution
× STOP mode held
× Reset processing
User’s Manual U18698EJ1V0UD
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