UPD78F0411GA-GAM-AX Datasheet, PDF (322/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 13 SERIAL INTERFACE UART0
(3) Baud rate generator control register 0 (BRGC0)
This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter.
BRGC0 can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 1FH.
Figure 13-4. Format of Baud Rate Generator Control Register 0 (BRGC0)
Address: FF71H After reset: 1FH R/W
Symbol
7
6
5
BRGC0
TPS01
TPS00
0
4
MDL04
3
MDL03
2
MDL02
1
MDL01
0
MDL00
TPS01
0
0
1
1
TPS00
0
1
0
1
Base clock (fXCLK0) selection^{Note 1}
fPRS = 2 MHz
TM50 output^{Note 2}
fPRS = 5 MHz
fPRS = 8 MHz
fPRS/2
fPRS/2³
fPRS/2⁵
1 MHz
250 kHz
62.5 kHz
2.5 MHz
625 kHz
156.25 kHz
4 MHz
1 MHz
250 kHz
fPRS = 10 MHz
5 MHz
1.25 MHz
312.5 kHz
MDL04
MDL03
MDL02
MDL01
MDL00
k
Selection of 5-bit counter
output clock
0
0
×
×
×
× Setting prohibited
0
1
0
0
0
8 fXCLK0/8
0
1
0
0
1
9 fXCLK0/9
0
1
0
1
0
10 fXCLK0/10
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
0
1
0
26 fXCLK0/26
1
1
0
1
1
27 fXCLK0/27
1
1
1
0
0
28 fXCLK0/28
1
1
1
0
1
29 fXCLK0/29
1
1
1
1
0
30 fXCLK0/30
1
1
1
1
1
31 fXCLK0/31
Notes 1.
2.
If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
fPRS operating frequency varies depending on the supply voltage.
• VDD = 2.7 to 5.5 V: fPRS ≤ 10 MHz
• VDD = 1.8 to 2.7 V: fPRS ≤ 5 MHz
When selecting the TM50 output as the base clock, Start the operation of 8-bit timer/event counter 50
first and then enable the timer F/F inversion operation (TMC501 = 1).
Cautions 1. Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when rewriting the
MDL04 to MDL00 bits.
2. The baud rate value is the output clock of the 5-bit counter divided by 2.
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User’s Manual U18698EJ1V0UD